• IEIE Transactions on Smart Processing and Computing
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• v.4 no.5
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• pp.366-370
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• 2015

This paper proposes a method for improving a branch predictor for the extendable instruction set computer (EISC) processor. The original EISC branch predictor has several shortcomings: a small branch target buffer, absence of a global history, a one-bit local branch history, and unsupported prediction of branches following LERI, which is a special instruction to extend an immediate value. We adopt a G-share branch predictor and eliminate the existing shortcomings. We verified the new branch predictor on a field-programmable gate array with the Dhrystone benchmark. The newly proposed EISC branch predictor also accomplishes higher branch prediction accuracy than a conventional branch predictor.

• International Journal of Aeronautical and Space Sciences
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• v.13 no.2
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• pp.260-265
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• 2012

Satellite devices for fine attitude control of the Science & Technology Satellite-2 (STSAT-2). Based on the mission requirements of STSAT-2, the conventional analog-type sun sensors were found to be inadequate, motivating the development of a compact, fast and fine digital sun sensor (FDSS). The FDSS uses a CMOS image sensor and has an accuracy of less than 0.03degrees, an update rate of 5Hz and a weight of less than 800g. A pinhole-type aperture is substituted for the optical lens to minimize its weight. The target process speed is obtained by utilizing the Field Programmable Gate Array (FPGA), which acquires images from the CMOS sensor, and stores and processes the image data. The sensor accuracy is maintained by a rigorous centroid algorithm. This paper describes the FDSS designs, realizations, tests and calibration results.

• Proceedings of the KIEE Conference
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• 2011.07a
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• pp.1306-1307
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• 2011

Recently, the small scale photovoltaic (PV) electronic devices are drawing attention as the upcoming PV generation system. The PV system is commonly used in small scale PV applications such as LED lighting and cell phone. This paper proposes photovoltaic output sensorless (POS) maximum power point tracking (MPPT) control for a small scale charging system of PV-nickel metal hydride battery using field-programmable gate array (FPGA) controller. A converter is connected to a small scale PV cell and battery, and performs the POS MPPT at the battery terminal current instead of being at the PV cell output voltage and current. The FPGA controller and converter operate based on POS MPPT method. The experimental results show that the nickel metal hydride battery is charged by the maximum PV output power.

• Proceedings of the Korean Information Science Society Conference
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• 2003.04c
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• pp.283-285
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• 2003

We have developed an optimization algorithm based formulation for performing efficient time driven simultaneous place and route for FPGAS. Field programmable gate array(FPGAS) provide of drastically reducing the turn-around time for digital ICs, with a relatively small degradation in performance. For a variety of application specific Integrated circuit application, where time-to-market is most critical and the performance requirement do not mandate a custom or semicustom approach, FPGAS are an increasingly popular alternative. This has prompted a substantial amount of specialized synthesis and layout research focused on maximizing density, minimizing delay, and minimizing design time.

• Journal of Electrical Engineering and Technology
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• v.6 no.2
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• pp.233-238
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• 2011

In the present work, a new approach is proposed for via interconnects of semiconductor devices, where multi-wall carbon nanotubes (MWCNTs) are used instead of conventional metals. In order to implement a selective growth of carbon nanotubes (CNTs) for via interconnect, the buried catalyst method is selected which is the most compatible with semiconductor processes. The cobalt catalyst for CNT growth is pre-deposited before via hole patterning, and to achieve the via etch stop on the thin catalyst layer (ca. 3nm), a novel 2-step etch scheme is designed; the first step is a conventional oxide etch while the second step chemically etches the silicon nitride layer to lower the damage of the catalyst layer. The results show that the 2-step etch scheme is a feasible candidate for the realization of CNT interconnects in conventional semiconductor devices.

• ETRI Journal
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• v.33 no.1
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• pp.71-77
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• 2011

Up to 10% of the global population suffers from color vision deficiency (CVD) [1], especially deuteranomaly and protanomaly, the conditions in which it is difficult to discriminate between red and green hues. For those who suffer from CVD, their career fields are restricted, and their childhood education is frustrating. There are many optical eye glasses on the market to compensate for this disability. However, although they are attractive due to their light weight, wearing these glasses will decrease visual brightness and cause problems at night. Therefore, this paper presents a supplementary device that comprises a head-mounted display and an image sensor. With the aid of the image processing technique of digital color space adjustment implemented in a high-speed field-programmable gate array device, the users can enjoy enhanced vision through the display without any decrease in brightness.

• Journal of Power Electronics
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• v.18 no.4
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• pp.1037-1050
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• 2018

This paper presents a novel reconfigurable selective harmonic elimination technique to control harmonics over a wide range of Modulation Indexes (MI) in Multi-Level Inverter (MLI). In the proposed method, the region of the MI is divided into various sectors and expressions are formulated with different switching patterns for each of the sectors. A memetic BBO-MAS (Biogeography Based Optimization - Mesh Adaptive direct Search) optimization algorithm is proposed for solving the Selective Harmonic Elimination - Pulse Width Modulation (SHE-PWM) technique. An experimental prototype is developed using a Field Programmable Gate Array (FPGA) and their FFT spectrums are analyzed over a wide range of MI using a fluke power logger. Simulation and experimental results have validated the performance of the proposed optimization algorithms and the reconfigurable SHE-PWM technique. Further, the sensitivity of the harmonics has been analyzed considering non-integer variations in the magnitude of the input DC sources.

• Proceedings of the KIPE Conference
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• 2011.07a
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• pp.561-562
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• 2011

인 휠 모터를 이용하여 구동되는 전기차량은 각 모터의 동기 제어가 요구된다. 기존의 마이크로컨트롤러는 구동시킬 수 있는 모터의 개수가 제한되어 인 휠 모터를 이용하여 구동되는 전기차량과 같은 다축 제어 시스템에 적용하기가 어렵다. 따라서 본 논문에서는 FPGA(Field Programmable Gate Array)를 이용하여 4축 동기 SVPWM 기법을 구현하였으며, 시뮬레이션을 통하여 성능을 확인하였다.

• Journal of Electrical Engineering and Technology
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• v.10 no.4
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• pp.1682-1691
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• 2015

In this paper, a real time implementation of selective harmonic elimination pulse width modulation (SHEPWM) using Real Coded Genetic Algorithm (RGA), Particle Swarm Optimization technique (PSO) and a new technique known as Linearization Method (LM) for Single Phase Matrix Converter (SPMC) is designed and discussed. In the proposed technique, the switching frequency is fixed and the optimum switching angles are obtained using simple mathematical calculations. A MATLAB simulation was carried out, and FFT analysis of the simulated output voltage waveform confirms the effectiveness of the proposed method. An experimental setup was also developed, and the switching angles and firing pulses are generated using Field Programmable Gate Array (FPGA) processor. The proposed method proves that it is much applicable in the industrial applications by virtue of its suitability in real time applications.

• Journal of Power Electronics
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• v.14 no.6
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• pp.1139-1146
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• 2014

Digital signal processor (DSP) and field programmable gate array (FPGA) based concentrated control systems are designed for implementing CPS-SPWM strategies. The self-defined universal asynchronous receiver/transmitter (UART) protocol is used for communication between a master controller and an individual module controller via high speed links. Aimed at undesired pulse competition, this paper analyzes its generation mechanism and presents a new method for eliminating competition pulses with no time delay. Finally, the proposed concentrated controller is applied to a 10kV/10MVar distribution static synchronous compensator (DSTATCOM) industrial prototype. Experimental results show the accuracy and reliability of the concentrated controller, and verify the superiority of the proposed elimination method for competition pulses.