• Journal of Sensor Science and Technology
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• v.18 no.2
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• pp.168-172
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• 2009

In this paper, we present the carbon nanotube field-effect transistor(CNT-FET) with a double-gate structure. A Carbon nanotube film was aligned by the Langmuir-Blodgett technique and $SiN_x$ was deposited to protect from water, oxygen, and other contaminants. We measured the electrical characteristics of the proposed device as the function of the $V_{BG}$, $V_{TG}$. From this result, we can confirm that proposed device might be employed as a biosensor.

• Applied Chemistry for Engineering
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• v.9 no.1
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• pp.6-12
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• 1998

A FET(Field Effect Transistor) type dissolved $CO_2$ sensor based on Severinghaus type $CO_2$ sensor was fabricated by the photolithographic process. The sensor consists of Ag/AgCl reference electrode and membranes (hydrogel membrane and $CO_2$ gas permeable membrane) on the pH-ISFET base chip. Ag/AgCl reference electrode was fabricated as follows. Ag layer was thermally evaporated and then its upper surface was chemically chloridized into the AgCl. The hydrogel used as an internal electrolyte solution was fabricated by a photolithographic method using 2-hydroxyethyl methacrylate(HEMA) and acrylamide. $CO_2$ permeable membrane on the top of the hydrogel layer was formed by photolithographic process with UV-oligomer. The FET type $pCO_2$ sensor fabricated by photolithographic method showed good linearity within the concentration range of $10^{-3}{\sim}10^0mole/{\ell}$ of dissolved $CO_2$ in aqueous solution with high sensitivity.

• Journal of Sensor Science and Technology
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• v.4 no.2
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• pp.7-13
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• 1995

A new FET type semiconductor pressure sensor (PSFET : pressure sensitive field effect transistor) was fabricated and its operational characteristics were investigated. A ZnO thin film as a piezoelectric layer, $5000{\AA}$ thick, was deposited on a gate oxide of FET by RF magnetron sputtering. The deposition conditions to obtain a c-axis poling structure were substrate temperature of $300^{\circ}C$, RF power of 140watt, and working pressure of 5mtorr in Ar ambience. The fabricated PSFET device showed good linearity and stability in the applied pressure range($1{\times}10^{5}\;Pa{\sim}4{\times}10^{5}\;Pa$).

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.562-562
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• 2012

Recently, graphene and graphene-based materials such as graphene oxide (GO) or reduced graphene oxide (R-GO) draws a great attention for electronic devices due to their structures of one atomic layer of carbon hexagon that have excellent mechanical, electrical, thermal, optical properties and very high specific surface area that can be high potential for chemical functionalization. R-GO is a promising candidate because it can be prepared with low-cost from solution process by chemical oxidation and exfoliation using strong acids and oxidants to produce graphene oxide (GO) and its subsequent reduction. R-GO has been used as semiconductor or conductor materials as well as sensing layer for bio-molecules or ions. In this work, reduced graphene oxide field-effect transistor (R-GO FET) has been fabricated with ITO extended gate structure that has sensing area on ITO extended gate part. R-GO FET device was encapsulated by tetratetracontane (TTC) layer using thermal evaporation. A thermal annealing process was carried out at $140^{\circ}C$ for 4 hours in the same thermal vacuum chamber to remove defects in R-GO film before deposition of TTC at $50^{\circ}C$ with thickness of 200 nm. As a result of this process, R-GO FET device has a very high stability and durability for months to serve as a transducer for sensing applications.

• Journal of Convergence for Information Technology
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• v.11 no.9
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• pp.124-129
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• 2021

A time-interpolation technique has been applied to the conventional FLASH analog-to-digital converter (ADC) to increase a number of quantization level, thus it reduces not only a power dissipation, but also minimize an active chip area. In this work, we demonstrated 5-bit ADC which has 31 quantization levels consisting of 16 conventional voltage-mode comparators and 15 time-mode comparators. As a result, we have achieved about 48.4% voltage-mode comparator reductions. The ADC is fabricated in a 14nm fin Field-effect transistor (FinFET) process with an active die area of 0.0024 mm2 while consuming 0.82 mW through a 0.8 V supply. At 400-MS/s conversion rate, the ADC performs 28.03 dB SNDR (4.36 ENOB) at 21MHz input frequency.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.6
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• pp.1-7
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• 2004

We performed two-dimensional (20) computer-based modeling and simulation of FinFET by solving the coupled Poisson-Schrodinger equations quantum-mechanically in a self-consistent manner. The simulation results are carefully investigated for FinFET with gate length(Lg) varying from 10 to 80nm and with a Si-fin thickness($T_{fin}$) varying from 10 to 40nm. Current-voltage (I-V) characteristics are compared with the experimental data. Device optimization has been performed in order to suppress the short-channel effects (SCEs) including the sub-threshold swing, threshold voltage roll-off, drain induced barrier lowering (DIBL). The quantum-mechanical simulation is compared with the classical appmach in order to understand the influence of the electron confinement effect. Simulation results indicated that the FinFET is a promising structure to suppress the SCEs and the quantum-mechanical simulation is essential for applying nano-scale device structure.

• Vacuum Magazine
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• v.3 no.3
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• pp.15-18
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• 2016

In future wearable electronic systems, 3-dimensional (3D) devices have attracted much attention due to their high density integration and low-power functionality. Among 3D devices, gate-all-around (GAA) nanowire transistor provides superior gate controllability, resulting in suppressing short channel effect and other drawbacks in 2D metal-oxide-semiconductor field-effect transistor (MOSFET). Silicon nanowires (SiNWs) are the most promising building block for GAA structure device due to their compatibility with the current Si-based ultra large scale integration (ULSI) technology. Moreover, the theoretical limit for subthreshold swing (SS) of MOSFET is 60 mV/dec at room temperature, which causes the increase in Ioff current. To overcome theoretical limit for the SS, it is crucial that research into new types of device concepts should be performed. In our present studies, we have experimentally demonstrated feedback FET (FBFET) and tunnel FET (TFET) with sub-60 mV/dec based on SiNWs. Also, we fabricated SiNW based complementary TFET (c-TFET) and SiNW complementary metal-oxide-semiconductor (CMOS) inverter. Our research demonstrates the promising potential of SiNW electronic devices for future wearable electronic systems.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.20 no.5
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• pp.394-398
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• 2007

A simple doping method to fabricate a very thin channel body of the nano-scaled n-type fin field-effect-transistor (FinFET) by arsenic solid-Phase-diffusion (SPD) process is presented. Using the As-doped spin-on-glass films and the rapid thermal annealing for shallow junction, the n-type source-drain extensions with a three-dimensional structure of the FinFET devices were doped. The junction properties of arsenic doped regions were investigated by using the $n^+$-p junction diodes which showed excellent electrical characteristics. The n-type FinFET devices with a gate length of 20-100 nm were fabricated by As-SPD and revealed superior device scalability.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.08a
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• pp.252-252
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• 2011

최근 주목받고 있는 amorphous gallium-indium-zinc-oxide (a-GIZO) thin film transistors (TFTs)는 수소가 첨가된 비정질 실리콘 TFT에 비해 높은 이동도와 뛰어난 전기적, 광학적 특성에 의해 큰 주목을 받고 있다. 또한 넓은 밴드갭을 가지므로 가시광 영역에서 투명한 특성을 보이고, 플라스틱 기판 위에서 구부러지는 성질에 의해 플랫 패널 디스플레이나 능동 유기 발광소자 (AM-OLED), 투명 디스플레이에 응용되고 있다. 뿐만 아니라, 일반적인 Poly-Si TFT는 자체적으로 가지는 결정성에 의해 대면적화 시 균일성이 좋지 못하지만 GIZO는 비정질상 이기 때문에 백플레인의 대면적화에 유리하다는 장점이 있다. 이러한 TFT를 제작하기 전, 전기적 특성에 대한 정보를 얻거나 예측하는 것이 중요한데, 이에 따라 고안된 구조가 바로 metal point contact FET (pseudo FET)이다. pseudo FET은 소스/드레인 전극을 따로 증착할 필요 없이 채널을 증착한 후, 프로브 탐침을 채널의 표면에 적당한 압력으로 접촉시켜 전하를 공급하는 소스와 드레인처럼 동작시킬 수 있다. 따라서 소스/드레인을 증착하거나 lithography와 같은 추가적인 공정을 요구하지 않아 소자의 특성을 보다 간단하고 수월하게 분석할 수 있다는 장점이 있다. 본 연구에서는 p-type 기판위에 100nm의 oxidation SiO2를 게이트 절연막으로 사용하는 a-GIZO pseudo FET를 제작하였다. 소자 제작 후, 열처리 온도에 따른 전기적 특성을 분석하였고, 열처리 조건은 30분간 N2 분위기에서 실시하였다. 열처리 후 전기적 특성 분성 결과, 450oC에서 가장 낮은 subthreshold swing 값과 게이트 전압의 더블 스윕 후 문턱 전압의 변화가 거의 없음을 확인하였다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.24 no.2
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• pp.321-324
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• 2020

In this work, we developed a selective etching process for GaN that is a key process in p-GaN/AlGaN/GaN enhancement-mode (E-mode) power switching field-effect transistor (FET) fabrication. In order to achieve a high current density of p-GaN/AlGaN/GaN E-mode FET, the p-GaN layer beside the gate region must be selectively etched whereas the underneath AlGaN layer should be maintained. A selective etching process was implemented by oxidizing the surface of the AlGaN layer and the GaN layer by adding O2 gas to Cl2/N2 gas which is generally used for GaN etching. A selective etching process was optimized using Cl2/N2/O2 gas mixture and a high selectivity of 53:1 (= GaN/AlGaN) was achieved.