• Journal of Power Electronics
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• 제10권3호
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• pp.228-234
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• 2010

This paper investigates the conducted-noise characteristics of a digitally-controlled randomly-switched dc-dc converter. In order to investigate the effect of the suggested digital controller on the conducted-noise characteristics of a dc-dc converter, three factors have been studied: the field-programmable gate array (FPGA) clock speed, the randomization ratio percentage, and the effect of using a closed loop feedback controller. A field-programmable gate array is much more flexible than analog control circuits, has a lower cost, and can be used for power supply applications. A novel FPGA-based implementation has been suggested for obtaining the experimental validations and realizing the studied concepts. Furthermore, the experimental results have been discussed and design guidelines have been included.

• Nuclear Engineering and Technology
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• 제44권6호
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• pp.697-708
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• 2012

The majority of instrumentation and control (I&C) systems in today's nuclear power plants (NPPs) are based on analog technology. Thus, most existing I&C systems now face obsolescence problems. Existing NPPs have difficulty in repairing and replacing devices and boards during maintenance because manufacturers no longer produce the analog devices and boards used in the implemented I&C systems. Therefore, existing NPPs are replacing the obsolete analog I&C systems with advanced digital systems. New NPPs are also adopting digital I&C systems because the economic efficiencies and usability of the systems are higher than the analog I&C systems. Digital I&C systems are based on two technologies: a microprocessor based system in which software programs manage the required functions and a programmable logic device (PLD) based system in which programmable logic devices, such as field programmable gate arrays, manage the required functions. PLD based systems provide higher levels of performance compared with microprocessor based systems because PLD systems can process the data in parallel while microprocessor based systems process the data sequentially. In this research, a bistable trip logic in a reactor protection system (RPS) was developed using very high speed integrated circuits hardware description language (VHDL), which is a hardware description language used in electronic design to describe the behavior of the digital system. Functional verifications were also performed in order to verify that the bistable trip logic was designed correctly and satisfied the required specifications. For the functional verification, a random testing technique was adopted to generate test inputs for the bistable trip logic.

• Journal of Electrical Engineering and Technology
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• 제11권5호
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• pp.1466-1474
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• 2016

• Journal of Power Electronics
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• 제11권2호
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• pp.218-227
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• 2011

The subject of variable step size maximum power point tracking (MPPT) algorithms has been addressed in the literature. However, most of the addressed algorithms tune the variable step size according to two variables: the photovoltaic (PV) array voltage ($V_{PV}$) and the PV array current ($I_{PV}$). Therefore, both the PV array current and voltage have to be measured. Recently, maximum power point trackers that arc based on a single variable ($I_{PV}$ or $V_{PV}$) have received a great deal of attention due to their simplicity and ease of implementation, when compared to other tracking techniques. In this paper, two methods have been proposed to design a variable step size MPPT algorithm using only a single current sensor for stand-alone battery storage PV systems. These methods utilize only the relationship between the PV array measured current and the converter duty cycle (D) to automatically adapt the step change in the duty cycle to reach the maximum power point (MPP) of the PV array. Detailed analyses and flowcharts of the proposed methods are included. Moreover, a comparison has been made between the proposed methods to investigate their performance in the transient and steady states. Finally, experimental results with field programmable gate arrays (FPGAs) are presented to verify the performance of the proposed methods.

• Nuclear Engineering and Technology
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• 제49권8호
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• pp.1589-1599
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• 2017

Field programmable gate arrays (FPGAs) are getting more attention in safety-related and safety-critical application development of nuclear power plant instrumentation and control systems. The high logic density and advancements in architectural features make static random access memory (SRAM)-based FPGAs suitable for complex design implementations. Devices deployed in the nuclear environment face radiation particle strike that causes transient and permanent failures. The major reasons for failures are total ionization dose effects, displacement damage dose effects, and single event effects. Different from the case of space applications, soft errors are the major concern in terrestrial applications. In this article, a review of radiation effects on FPGAs is presented, especially soft errors in SRAM-based FPGAs. Single event upset (SEU) shows a high probability of error in the dependable application development in FPGAs. This survey covers the main sources of radiation and its effects on FPGAs, with emphasis on SEUs as well as on the measurement of radiation upset sensitivity and irradiation experimental results at various facilities. This article also presents a comparison between the major SEU mitigation techniques in the configuration memory and user logics of SRAM-based FPGAs.

• Nuclear Engineering and Technology
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• 제54권11호
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• pp.3985-3995
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• 2022

The emergence of new nanoscale technologies has imposed significant challenges to designing reliable electronic systems in radiation environments. A few types of radiation like Total Ionizing Dose (TID) can cause permanent damages on such nanoscale electronic devices, and current state-of-the-art technologies to tackle TID make use of expensive radiation-hardened devices. This paper focuses on a novel and different approach: using machine learning algorithms on consumer electronic level Field Programmable Gate Arrays (FPGAs) to tackle TID effects and monitor them to replace before they stop working. This condition has a research challenge to anticipate when the board results in a total failure due to TID effects. We observed internal measurements of FPGA boards under gamma radiation and used three different anomaly detection machine learning (ML) algorithms to detect anomalies in the sensor measurements in a gamma-radiated environment. The statistical results show a highly significant relationship between the gamma radiation exposure levels and the board measurements. Moreover, our anomaly detection results have shown that a One-Class SVM with Radial Basis Function Kernel has an average recall score of 0.95. Also, all anomalies can be detected before the boards are entirely inoperative, i.e. voltages drop to zero and confirmed with a sanity check.

• KSII Transactions on Internet and Information Systems (TIIS)
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• 제11권5호
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• pp.2680-2700
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• 2017

Finite field arithmetic over GF($2^m$) is used in a variety of applications such as cryptography, coding theory, computer algebra. It is mainly used in various cryptographic algorithms such as the Elliptic Curve Cryptography (ECC), Advanced Encryption Standard (AES), Twofish etc. The multiplication in a finite field is considered as highly complex and resource consuming operation in such applications. Many algorithms and architectures are proposed in the literature to obtain efficient multiplication operation in both hardware and software. In this paper, a modified serial multiplication algorithm with interleaved modular reduction is proposed, which allows for an efficient realization of a sequential polynomial basis multiplier. The proposed sequential multiplier supports multiplication of any two arbitrary finite field elements over GF($2^m$) for generic irreducible polynomials, therefore made versatile. Estimation of area and time complexities of the proposed sequential multiplier is performed and comparison with existing sequential multipliers is presented. The proposed sequential multiplier achieves 50% reduction in area-delay product over the best of existing sequential multipliers for m = 163, indicating an efficient design in terms of both area and delay. The Application Specific Integrated Circuit (ASIC) and the Field Programmable Gate Array (FPGA) implementation results indicate a significantly less power-delay and area-delay products of the proposed sequential multiplier over existing multipliers.

• ETRI Journal
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• 제39권4호
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• pp.570-581
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• 2017

Multiplication in finite fields is used in many applications, especially in cryptography. It is a basic and the most computationally intensive operation from among all such operations. Several systolic multipliers are proposed in the literature that offer low hardware complexity or high speed. In this paper, a bit-parallel polynomial basis systolic multiplier for generic irreducible polynomials is proposed based on a modified interleaved multiplication method. The hardware complexity and delay of the proposed multiplier are estimated, and a comparison with the corresponding multipliers available in the literature is presented. Of the corresponding multipliers, the proposed multiplier achieves a reduction in the hardware complexity of up to 20% when compared to the best multiplier for m = 163. The synthesis results of application-specific integrated circuit and field-programmable gate array implementations of the proposed multiplier are also presented. From the synthesis results, it is inferred that the proposed multiplier achieves low power consumption and low area complexitywhen compared to the best of the corresponding multipliers.

• 한국항행학회논문지
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• 제21권4호
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• pp.386-393
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• 2017

칩을 개발하는 과정에서 설계된 칩의 검증을 위해 FPGA (field programmable gate array)를 많이 이용한다. FPGA에 다운로드 된 회로를 검증하기 위해서는 FPGA로 데이터를 입력해야 한다. PC와 외부 보드를 통한 칩과의 통신을 위한 많은 방식이 있지만 가장 간단하고 쉬운 방법은 범용 비동기화 송수신기 (UART; universal asynchronous receiver/transmitter)를 이용한 방식이다. 최근 대부분의 회로는 AMBA (advanced microcontroller bus architecture) 버스에 연결되도록 설계되어 있다. 즉, 설계된 회로를 검증하기 위해서는 UART를 거친 후에 AMBA 버스를 통해 데이터를 전달해야 한다. AMBA 버스도 최근에 버전 4.0까지 거치면서 다양한 버전이 존재하는데 간단히 테스트를 하기 위한 용도로는 APB (advanced peripheral bus)가 적합하다. 본 논문에서는 UART-to-APB 인터페이스를 위한 회로를 설계하였다. Verilog HDL을 이용하여 설계된 회로는 Altera Cyclone FPGA에서 구현되었고, 최대 380 MHz의 속도에서 동작이 가능하였다.

• 전자공학회논문지A
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• 제32A권10호
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• pp.93-101
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• 1995

The evaluation of the logic capability and the library generation method of the multiplexor-based logic module is described. Optimizing logic module for silicon area and logic capability is essential to build a efficient FPGAs(Field-Programmable Gate Arrays). Because the multiplexor-based logic module can implement a large number of functions, it presents difficulties for library-based approaches. However, the logic functions of the logic module can be significantly reduced by lmiting the number of variables and sum-of-products and by removing same functions with different variable ordering using algorithm presented in this paper.