1 |
Çavuşlu MA, Altun H and Karakaya F, “Plaka Yeri Tespiti İçin Kenar Bulma, Bit Tabanlı Öznitelik Çıkartma ve YSA Sınıflandırıcısının FPGA Üzerine Uyarlanması,” GomSis 2008.
|
2 |
Goldstein SC, Schmit H, Budiu M, Cadambi S, Moe M and Taylor RR, “PipeRench: a Reconfigurable Architecture and Compiler,” Computer, 33(4), 70-77, 2000.
DOI
|
3 |
Crookes D, Benkrid K, Bouridane A, Aiotaibi K and Benkrid A, “Design and implementation of a high level programming environment for FPGA-based image processing,” IEE P-Vis Image Sign, 147, 377-384, 2000.
DOI
|
4 |
Harkin J, McGinnityand TM and Maguire LP, “Partitioning methodology for dynamically reconfigurable embedded systems,” IEE P-Comput Dig T, 147, 391-396, 2000.
DOI
|
5 |
Goda BS, McDonald JF, Carlough SR, KrawczykJr TW and Kraft RP, “SiGe HBT BiCMOS FPGAs for fast reconfigurable computing,” IEE P-Comput Dig T, 147(3), 189-194, 2000.
DOI
|
6 |
Koyuncu İ, “A Matrix Multiplication Engine for Graphic Systems Designed to run on FPGA Devices,” MS Thesis, Duzce University, 2008.
|
7 |
Hauck S, “The Roles of FPGA’s in Reprogrammable Systems,” P IEEE, 86(4), 615-638, 1998.
DOI
|
8 |
Sahin I and Koyuncu I, “Design and Implementation of Neural Networks Neurons with RadBas, LogSig, and TanSig Activation Functions on FPGA,” Elektron Elektrotech 4(120), 51-54, 2012.
|
9 |
Çavuşlu MA, Karakuzu C, Şahin S and Karakaya F, “Yapay Sinir Ağı Eğitiminin IEEE 754 Kayan Noktalı Sayı Formatı İle FPGA Tabanlı Gerçeklenmesi,” GomSis, 2008.
|
10 |
Tamulevičius G, Arminas V, Ivanovas E and Navakauskas D, “Hardware Accelerated FPGA Implementation of Lithuanian Isolated Word Recognition System,” Elektron Elektrotech, 3(99), 52-62, 2010.
|
11 |
Polata Ö and Yıldırım T, “FPGA implementation of a General Regression Neural Network: An embedded pattern classification system,” Digital Signal Process, 20, 881-886, 2010.
DOI
|
12 |
Sahin İ, “A 32-Bit Floating-Point Module Design for 3D Graphic Transformations,” Sci Res Essays, 5(20), 3070-3081, 2010.
|
13 |
Gomperts A, Ukil A and Zurfluh F, “Development and Implementation of Parameterized FPGA-Based General Purpose Neural Networks for Online Applications,” IEEE T Ind Inform, 7(1), 72-88, 2011.
|
14 |
Chorowski J and Zurada JM, “Extracting Rules from Neural Networks as Decision Diagrams,” IEEE T Neural Network, 99, 1-12, 2011.
|
15 |
Yildiz O, “Döviz Kuru Tahmininde Yapay Sinir Ağlarının Kullanımı,” MS Thesis, Eskisehir Osmangazi University, 2006.
|
16 |
Sahin I, “A Compilation Tool for Automated Mapping of Algorithms onto FPGA Based Custom Computing Machines,” Dissertation, North Carolina State University, Raleigh-USA, 2002.
|
17 |
Levinskis A, “Convolutional Neural Network Feature Reduction using Wavelet Transform,” Elektron Elektrotech, 19(3), 61-64, 2013.
|
18 |
Gupta V, Khare K and Singh RP, “FPGA Design and Implementation Issues of Artificial Neural Network Based PID Controllers,” Proc. ARTCOM ’09, 860-862, 2009.
|
19 |
Togawa N, Yanagisawa M and Ohtsuki T, “Mapleopt: A Performance-Oriented Simultaneous Technology Mapping, Placement, and Global Routing Algorithm for FPGA’s,” IEEE T Comput Aid D, 17(9), 803-818, 1998.
DOI
|
20 |
Diessel O and Milne G, “Hardware compiler realizing concurrent processes in reconfigurable logic,” IEE Proc.-Comput. Digit. Tech., 148-4/5, 152-162, 2001.
DOI
|
21 |
Zulfikar MY, Abbasi SA and Alamoud ARM, “FPGA Based Walsh and Inverse Walsh Transforms for Signal Processing,” Elektron Elektrotech, 18(8), 3-8, 2012.
|
22 |
Lin Z, Dong Y, Li Y and Watanabe T, “A Hybrid Architecture for Efficient FPGA-based Implementation of Multilayer Neural Networks,” IEEE Circuits and Systems (APCCAS), 616-619, 2011
|
23 |
Bastos JL, Figueroa HP and Monti A, “FPGA implementation of neural network-based controllers for power electronics applications,” IEEE Twenty-First page Annual Applied Power Electronics Conference and Exposition, 1443-1448, 2006.
|
24 |
Benrekia F, Attari M, Bermak A and Belhout K, “FPGA implementation of a neural network classifier for gas sensor array applications,” 6th International Multi-Conference on Systems, Signals and Devices, 1-6 2009.
|
25 |
Weinstein RK and Lee H, “Architectures for high-performance FPGA implementations of neural models,” J Neural Eng, 3, 1-21, 2006.
DOI
|
26 |
Uçar A, “FPGA implementation of a neural network for Turkish phoneme classification,” MS Thesis, Hacettepe University, 2007.
|
27 |
Funabiki N, Yoda M, Kitamichi J and Nishikawa S, “A gradual neural network approach for FPGA segmented channel routing problems,” IEEE T Syst Man Cy B, 29, 481-489, 1999.
|
28 |
Sahin I and Akkaya A, “ANNDES: An artificial neural network design and education software,” ICITS 2011 5th International Computer and Instructional Technologies Symposium, 2011.
|