• Title/Summary/Keyword: Field Programmable Gate Array

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Circuit Partitioning Using A New Quadratic Boolean Programming Formulation for Reconfigurable Circuit Boards (재구성 가능한 회로 보드를 위한 새로운 Quadratic Boolean Programming 수식에 의한 분할)

  • Choe, Yeon-Gyeong;Im, Jong-Seok
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.37 no.2
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    • pp.65-77
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    • 2000
  • We propose a new formulation by quadratic boolean programming to partition circuits for FPGA based reconfigurable circuit boards, in which the routing topology among IC chips are predetermined. The formulation is to minimize the sum of the wire length by considering the nets passing through IC chips for the interconnections between chips which are not adjacent, in addition to the constraints considered by the previous partition methods. We also describe a heuristic method, which consist of module assignment method to efficiently solve the problem. Experimental results show that our method generates the partitions in which the given constraints are all satisfied for all the benchmark circuits tested. The pin utilization are reduced for the most of the circuits and the total wire length of the routed nets are improved up to 34.7% compared to the previous method.

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A Study on Design of Evolving Hardware using Field Programmable Gate Array (FPGA를 이용한 진화형 하드웨어 설계 및 구현에 관한 연구)

  • 반창봉;곽상영;이동욱;심귀보
    • Journal of the Korean Institute of Intelligent Systems
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    • v.11 no.5
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    • pp.426-432
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    • 2001
  • This paper is implementation of cellular automata neural network system using evolving hardware concept. This system is a living creatures'brain based on artificial life techniques. Cellular automata neural network system is based on the development and the evolution, in other words, it is modeled on the ontogeny and phylogney of natural living things. The phylogenetic mechanism are fundamentally non-deterministic, with the mutation and recombination rate providing a major source of diversity. Ontogeny is deterministic and local physics. Cellular automata is developed from initial cells, and evaluated in given environment. And genetic algorithms take a part in adaptation process. In this paper we implement this system using evolving hardware concept. Evolving hardware is reconfigurable hardware whose configuration si under the control of an evolutionary algorithm. We design genetic algorithm process for evolutionary algorithm and cells in cellular automata neural network for the construction of reconfigurable system. The effectiveness of the proposed system if verified by applying it to Exclusive-OR.

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FPGA Modem Platform Design for eHSPA and Its Regularized Verification Methodology (eHSPA 규격을 만족하는 FPGA모뎀 플랫폼 설계 및 검증기법)

  • Kwon, Hyun-Il;Kim, Kyung-Ho;Lee, Chung-Yong
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.46 no.2
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    • pp.24-30
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    • 2009
  • In this paper, the FPGA modem platform complying with 3GPP Release 7 eHSPA specifications and its regularized verification flow are proposed. The FFGA platform consists of modem board supporting physical layer requirements, MCU and DSP core embedded control board to drive the modem board, and peripheral boards for RF interfacing and various equipment interfaces. On the other hand, the proposed verification flow has been regularized into three categories according to the correlation degrees of hardware-software inter-operation, such as simple function test, scenario test call processing and system-level performance test. When it comes to real implementations, the emulation verification strategy for low power mobile SoC is also introduced.

Toward Optimal FPGA Implementation of Deep Convolutional Neural Networks for Handwritten Hangul Character Recognition

  • Park, Hanwool;Yoo, Yechan;Park, Yoonjin;Lee, Changdae;Lee, Hakkyung;Kim, Injung;Yi, Kang
    • Journal of Computing Science and Engineering
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    • v.12 no.1
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    • pp.24-35
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    • 2018
  • Deep convolutional neural network (DCNN) is an advanced technology in image recognition. Because of extreme computing resource requirements, DCNN implementation with software alone cannot achieve real-time requirement. Therefore, the need to implement DCNN accelerator hardware is increasing. In this paper, we present a field programmable gate array (FPGA)-based hardware accelerator design of DCNN targeting handwritten Hangul character recognition application. Also, we present design optimization techniques in SDAccel environments for searching the optimal FPGA design space. The techniques we used include memory access optimization and computing unit parallelism, and data conversion. We achieved about 11.19 ms recognition time per character with Xilinx FPGA accelerator. Our design optimization was performed with Xilinx HLS and SDAccel environment targeting Kintex XCKU115 FPGA from Xilinx. Our design outperforms CPU in terms of energy efficiency (the number of samples per unit energy) by 5.88 times, and GPGPU in terms of energy efficiency by 5 times. We expect the research results will be an alternative to GPGPU solution for real-time applications, especially in data centers or server farms where energy consumption is a critical problem.

Implementation of CCSDS Telecommand Decryptor in Geostationary Communications Satellite (정지궤도 통신위성의 CCSDS 원격명령 암호복호기 구현)

  • Kim,Jung-Pyo;Gu,Cheol-Hoe;Choe,Jae-Dong
    • Journal of the Korean Society for Aeronautical & Space Sciences
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    • v.31 no.10
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    • pp.89-96
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    • 2003
  • In this paper, a CCSDS(Consultative Committee for Space Data Systems) telecommand(TC) decryptor for the security of geostationary communications satellite was implemented. For the confidentiality of CCSDS TC datalink security, Option-A which implements the security services below the transfer sublayer was selected. Also CFB(Cipher Feedback) operation mode of DES(Data Encryption Standard) was used for the encryption of 56-bit data bits in 64-bit codeblock. To verify Decryptor function, the DES CFB logic implemented on A54SX32 FPGA(Field Programmable Gate Array) was integrated with interface and control logics in a PCB(Printed Circuit Board). Using a function test PC, the encrypted codeblocks were generated, transferred into the decryptor, decrypted, and the decrypted codeblocks were transmitted to the function test PC, and then compared with the source codeblocks. Through LED(Light Emitting Diode) ON operation by driving the relay related to Op-code decoded and the comparison between the codeblock output waveforms measured and those simulated, the telecommand decryptor function was verified.

Development of STSAT-2 Ground Station Baseband Control System (과학기술위성2호 지상관제를 위한 기저대역 제어 시스템 개발)

  • O, Seung-Han;O, Dae-Su
    • Journal of the Korean Society for Aeronautical & Space Sciences
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    • v.34 no.1
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    • pp.110-115
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    • 2006
  • STSAT-2 is the first satellite which will be launched by the first Korean Space Launch Vehicle(KSLV). Ground station Baseband Control system(GBC) is now developed for STSAT-2. GBC has two functions. One is control data path between satellite control computers and ground station antennas(1.5M, 3.7M, 13M) automatically. The other is sending and receiving data between ground station and satellite. GBC is implemented by FPGA(Field-Programmable Gate Array) which includes almost all logic(for MODEM, PROTOCOL and GBC system control). MODEM in GBC has two uplink FSK modulators(1.2[kbps], 9.6[kbps]) and six downlink FSK demodulators(9.6[kbps], 38.4[kbps]). In hardware, STSAT-2 GBC is smaller than STSAT-1 GBC. In function, STSAT-2 GBC has more features than STSAT-1 GBC. This paper is about GBC structure, functions and test results.

Experimental Verification of Heat Sink for FPGA Thermal Control (FPGA 열제어용 히트싱크 효과의 실험적 검증)

  • Park, Jin-Han;Kim, Hyeon-Soo;Ko, Hyun-Suk;Jin, Bong-Cheol;Seo, Hak-Keum
    • Journal of the Korean Society for Aeronautical & Space Sciences
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    • v.42 no.9
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    • pp.789-794
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    • 2014
  • The FPGA is used to the high speed digital satellite communication on the Digital Signal Process Unit of the next generation GEO communication satellite. The high capacity FPGA has the high power dissipation and it is difficult to satisfy the derating requirement of temperature. This matter is the major factor to degrade the equipment life and reliability. The thermal control at the equipment level has been worked through thermal conduction in the space environment. The FPGA of CCGA or BGA package type was mounted on printed circuit board, but the PCB has low efficient to the thermal control. For the FPGA heat dissipation, the heat sink was applied between part lid and housing of equipment and the performance of heat sink was confirmed via thermal vacuum test under the condition of space qualification level. The FPGA of high power dissipation has been difficult to apply for space application, but FPGA with heat sink could be used to space application with the derating temperature margin.

Hardware Channel Decoder for Holographic WORM Storage (홀로그래픽 WORM의 하드웨어 채널 디코더)

  • Hwang, Eui-Seok;Yoon, Pil-Sang;Kim, Hak-Sun;Park, Joo-Youn
    • Transactions of the Society of Information Storage Systems
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    • v.1 no.2
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    • pp.155-160
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    • 2005
  • In this paper, the channel decoder promising reliable data retrieving in noisy holographic channel has been developed for holographic WORM(write once read many) system. It covers various DSP(digital signal processing) blocks, such as align mark detector, adaptive channel equalizer, modulation decoder and ECC(error correction code) decoder. The specific schemes of DSP are designed to reduce the effect of noises in holographic WORM(H-WORM) system, particularly in prototype of DAEWOO electronics(DEPROTO). For real time data retrieving, the channel decoder is redesigned for FPGA(field programmable gate array) based hardware, where DSP blocks calculate in parallel sense with memory buffers between blocks and controllers for driving peripherals of FPGA. As an input source of the experiments, MPEG2 TS(transport stream) data was used and recorded to DEPROTO system. During retrieving, the CCD(charge coupled device), capturing device of DEPROTO, detects retrieved images and transmits signals of them to the FPGA of hardware channel decoder. Finally, the output data stream of the channel decoder was transferred to the MPEG decoding board for monitoring video signals. The experimental results showed the error corrected BER(bit error rate) of less than $10^{-9}$, from the raw BER of DEPROTO, about $10^{-3}$. With the developed hardware channel decoder, the real-time video demonstration was possible during the experiments. The operating clock of the FPGA was 60 MHz, of which speed was capable of decoding up to 120 mega channel bits per sec.

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Heterogeneous Sensor Data Analysis Using Efficient Adaptive Artificial Neural Network on FPGA Based Edge Gateway

  • Gaikwad, Nikhil B.;Tiwari, Varun;Keskar, Avinash;Shivaprakash, NC
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.13 no.10
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    • pp.4865-4885
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    • 2019
  • We propose a FPGA based design that performs real-time power-efficient analysis of heterogeneous sensor data using adaptive ANN on edge gateway of smart military wearables. In this work, four independent ANN classifiers are developed with optimum topologies. Out of which human activity, BP and toxic gas classifier are multiclass and ECG classifier is binary. These classifiers are later integrated into a single adaptive ANN hardware with a select line(s) that switches the hardware architecture as per the sensor type. Five versions of adaptive ANN with different precisions have been synthesized into IP cores. These IP cores are implemented and tested on Xilinx Artix-7 FPGA using Microblaze test system and LabVIEW based sensor simulators. The hardware analysis shows that the adaptive ANN even with 8-bit precision is the most efficient IP core in terms of hardware resource utilization and power consumption without compromising much on classification accuracy. This IP core requires only 31 microseconds for classification by consuming only 12 milliwatts of power. The proposed adaptive ANN design saves 61% to 97% of different FPGA resources and 44% of power as compared with the independent implementations. In addition, 96.87% to 98.75% of data throughput reduction is achieved by this edge gateway.

Real-time 3D Converting System using Stereoscopic Video (스테레오 비디오를 이용한 실시간 3차원 입체 변환 시스템)

  • Seo, Young-Ho;Choi, Hyun-Jun;Kim, Dong-Wook
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.33 no.10C
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    • pp.813-819
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    • 2008
  • In this paper, we implemented a real-time system which displays 3-dimensional (3D) stereoscopic image with stereo camera. The system consists of a set of stereo camera, FPGA board, and 3D stereoscopic LCD. Two CMOS image sensor were used for the stereo camera. FPGA which processes video data was designed with Verilog-HDL, and it can accommodate various resolutional videos. The stereoscopic image is configured by two methods which are side-by-side and up-down image configuration. After the left and right images are converted to the type for the stereoscopic display, they are stored into SDRAM. When the next frame is inputted into FPGA from two CMOS image sensors, the previous video data is output to the DA converter for displaying it. From this pipeline operation, the real-time operation is possible. After the proposed system was implemented into hardware, we verified that it operated exactly.