• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.1
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• pp.46-52
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• 2012

Separate extraction of source ($R_S$) and drain ($R_D$) resistances caused by process, layout variations and long term degradation is very important in modeling and characterization of MOSFETs. In this work, we propose "Avalanche Hot-Source Method (AHSM)" for simple separated extraction of $R_S$ and $R_D$ in a single device. In AHSM, the high field region near the drain works as a new source for abundant carriers governing the current-voltage relationship in the MOSFET at high drain bias. We applied AHSM to n-channel MOSFETs as single-finger type with different channel width/length (W/L) combinations and verified its usefulness in the extraction of $R_S$ and $R_D$. We also confirmed that there is a negligible drift in the threshold voltage ($V_T$) and the subthreshold slope (SSW) even after application of the method to devices under practical conditions.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.10
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• pp.2154-2162
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• 2009

This paper describes a scalar multiplier for Elliptic curve cryptography for smart card security. The scaler multiplier has 163-bits key size which supports the specifications of smart card standard. To reduce the computational complexity of scala multiplication on finite field, the non-adjacent format (NAF) conversion algorithm which is based on complementary recoding is adopted. The scalar multiplier core synthesized with a 0.35-${\mu}m$ CMOS cell library has 32,768 gates and can operate up to 150-MHz@3.3-V. It can be used in hardware design of Elliptic curve cryptography processor for smartcard security.

• The KIPS Transactions:PartA
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• v.11A no.2
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• pp.115-122
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• 2004

In this paper, the multiple-valued adders and multipliers are implemented by current-mode CMOS. First, we implement the 3-valued T-gate and the 4-valued T-gate using current-mode CMOS which have an effective availability of integrated circuit design. Second we implement the circuits to be realized 2-variable 3-valued addition table and multiplication table over finite fields $GF(3^2)$, and 2-variable 4-valued addition table and multiplication table over finite fields $GF(4^2)$ with the multiple-valued T-gates. Finally, these operation circuits are simulated under $1.5\mutextrm{m}$ CMOS standard technology, $15\mutextrm{A}$ unit current, and 3.3V VDD voltage Spice. The simulation results have shown the satisfying current characteristics. The 3-valued adder and multiplier, and the 4-valued adder and multiplier implemented by current-mode CMOS is simple and regular for wire routing and possesses the property of modularity with cell array. Also, since it is expansible for the addition and multiplication of two polynomials in the finite field with very large m, it is suitable for VLSI implementation.

• Journal of IKEEE
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• v.25 no.4
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• pp.625-633
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• 2021

This paper describes a scalable architecture for flexible hardware implementation of Montgomery modular multiplication. Our scalable modular multiplier architecture, which is based on a one-dimensional array of processing elements (PEs), performs word parallel operation and allows us to adjust computational performance and hardware complexity depending on the number of PEs used, N_PE. Based on the proposed architecture, we designed a scalable Montgomery modular multiplier (sMM) core supporting eight field sizes defined in SEC2. Synthesized with 180-nm CMOS cell library, our sMM core was implemented with 38,317 gate equivalents (GEs) and 139,390 GEs for N_PE=1 and N_PE=8, respectively. When operating with a 100 MHz clock, it was evaluated that 256-bit modular multiplications of 0.57 million times/sec for N_PE=1 and 3.5 million times/sec for N_PE=8 can be computed. Our sMM core has the advantage of enabling an optimized implementation by determining the number of PEs to be used in consideration of computational performance and hardware resources required in application fields, and it can be used as an IP (intellectual property) in scalable hardware design of elliptic curve cryptography (ECC).

• Journal of Plant Biotechnology
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• v.2 no.3
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• pp.151-155
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• 2000

Shoot proliferation was obtained from shoot tips and nodal explants of Vitex negundo L. on MS medium supplemented with either BAP or KIN (0.1-2.0 mg/L) alone or in combination with NAA (0.1 mg/L). The concentrations of cytokinins combined with NAA produced multiple shoots from shoot tips and nodal explants. The highest mean percentage (84.3$\pm$8.0) of shoot multiplication's were observed on nodal explants in the presence of BAP (1.5 mg/L) and NAA (0.1 mg/L) followed by shoot tips (65.0$\pm$5.0). The regenerated shootlets were rooted on MS basal medium IAA, IBA, NAA (0.1-1.5 mg/L). The maximum number of roots (51.0$\pm$2.6) was achieved on the medium containing IBA (1.0 mg/L) followed by other auxins (NAA, IAA). The regenerated plants were successfully transferred to a mixture of vermiculate and soil. About 95% of the plantlets survived when transferred to the field.

• Proceedings of the KIEE Conference
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• 1995.07c
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• pp.1385-1387
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• 1995

The Monte Carlo method for studying the steady-state behavior of electrons under the influence of a electric field is described. In this simulation used a Free Flight Time technique based on determination of the increase in kinetic energy between two collisions. The electron behavior in the cathode region of a corona discharge has been analysed using this method; spatial variations of the energy and excitation, ionization, and the multiplication of electrons were discussed.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.08a
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• pp.431-431
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• 2012

A compact tokamak reactor concept as a 14 MeV neutron source is desirable from an economic viewpoint for a fusion-driven transmutation reactor. LAR (Low Aspect Ratio) tokamak allows a potential of high "see full txt" operation with high bootstrap current fractions and can be used for a compact fusion neutron source. For the optimal design of a reactor, a radial build of reactor components has to be determined by considering the plasma physics and engineering constraints which inter-relate various reactor components and are constrained to use ITER physics and technology. In a transmutation reactor, the blanket should produce enough tritium for tritium self-sufficiency and the neutron multiplication factor, keff should be less than 0.95 to maintain sub-criticality. The shield should provide sufficient protection for the superconducting toroidal field (TF) coil against radiation damage and heating effects of the fusion neutrons, fission neutrons, and secondary gammas. In this work, characteristics of transmutation reactor based on LAR tokamak is investigated by using the coupled system analysis.

• Bulletin of the Korean Mathematical Society
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• v.52 no.4
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• pp.1327-1338
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• 2015

In this paper, we introduce and study the w-weak global dimension w-w.gl.dim(R) of a commutative ring R. As an application, it is shown that an integral domain R is a $Pr\ddot{u}fer$ v-multiplication domain if and only if w-w.gl.dim(R) ${\leq}1$. We also show that there is a large class of domains in which Hilbert's syzygy Theorem for the w-weak global dimension does not hold. Namely, we prove that if R is an integral domain (but not a field) for which the polynomial ring R[x] is w-coherent, then w-w.gl.dim(R[x]) = w-w.gl.dim(R).

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.771-774
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• 1998

In this paper proposes a new bit-parallel structure for a multiplier over GF((Pn)m), with k-nm. Mastrovito Multiplier, Karatsuba-ofman algorithm are applied to the multiplication of polynomials over GF(2n). This operation has a complexity of order O(k log p3) under certain constrains regardig k. A complete set of primitive field polynomials for composite fields is provided which perform modulo reduction with low complexity. As a result, multiplier for fields GF(Pk) with low gate counts and low delays are constructed. The architectures are highly modular and thus well suited for VLSI implementation.

• The Bulletin of The Korean Astronomical Society
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• v.40 no.2
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• pp.44.1-44.1
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• 2015

We set up a project to make spectrometers for single dish observations of the Korean VLBI Network (KVN), a new future multi-beam receiver of the ASTE (Atacama Submillimeter Telescope Experiment), and the total power (TP) antennas of the Atacama Large Millimeter/submillimeter Array (ALMA). Traditionally, spectrometers based on ASIC (Application-Specific Integrated circuit) and FPGA (Field-Programmable Gate Array) have been used in radio astronomy. It is, however, that a Graphics Processing Unit (GPU) technology is now viable for spectrometers due to the rapid improvement of its performance. A high-resolution spectrometer should have the following functions: poly-phase filter, data-bit conversion, fast Fourier transform, and complex multiplication. We wrote a program based on CUDA (Compute Unified Device Architecture) for a GPU spectrometer. We measured its performance using two GPU cards, Titan X and K40m, from NVIDIA. A non-optimized GPU code can process a data stream of around 2 GHz bandwidth, which is enough for the KVN spectrometer and promising for the ASTE and ALMA TP spectrometers.