• Title/Summary/Keyword: Feedback Circuit

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Design and Implementation of a Novel Frequency Modulation Circuit using Phase Locked Synthesizer (PLL Synthesizer를 이용한 새로운 FM 회로 설계 및 제작)

  • Yang, Seong-Sik;Lee, Jong-Hwan;Yeom, Kyung-Whan
    • Proceedings of the Korea Electromagnetic Engineering Society Conference
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    • 2003.11a
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    • pp.224-228
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    • 2003
  • In this paper, for phase lock loop(PLL) synthesizer, we introduce a novel but simple and low cost frequency modulation(FM) circuit of a flat peak frequency deviation for modulation signal from high to very low frequency penetrating into the loop-bandwidth of PLL. The FM circuit was basically designed to compensate an amount of feedback of the loop filter in PLL. The circuit also includes the capability of the adjustment of peak frequency deviation and blocking the interference with the loop filter. The designed circuit was successfully implemented and showed the flat frequency deviation as expected in the design.

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Testable Design for Zipper CMOS Circuits (고장 검풀이 용이한 Zipper CMOS 회로의 설계)

  • Seung Ryong Rho
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.24 no.3
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    • pp.517-526
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    • 1987
  • This paper proposes a new testable design for Zipper CMOS circuits. This design provides an additional feedback loop (called self oscillation loop) whichin the circuit, for testability. The circuit is tested only by observing the oscillation on the loop. The design can be applied to the multistage as well as the single stage, and can detect multiple faults which are undetectable by the conventional testing method. The application and evaluation of test patterns become easy and fault-free responses are not necessary. If the conventional testing method is applied to the sequential Zipper CMOS circuit with the LSSD design technique, it has the serious defect that the initial value may change due to intermediate test patterns and much time taken to apply the necessary test patterns. By using the proposed design, however, the sequential Zipper CMOS circuit with the LSSD design technique can be easily tested without such a defect. Also, the validity of the design is verified by performing the circuit level simulation.

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Integrate-and-Fire Neuron Circuit and Synaptic Device with Floating Body MOSFETs

  • Kwon, Min-Woo;Kim, Hyungjin;Park, Jungjin;Park, Byung-Gook
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.14 no.6
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    • pp.755-759
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    • 2014
  • We propose an integrate-and-fire neuron circuit and synaptic devices with the floating body MOSFETs. The synaptic devices consist of a floating body MOSFET to imitate biological synaptic characteristics. The synaptic learning is performed by hole accumulation. The synaptic device has short-term and long-term memory in a single silicon device. I&F neuron circuit emulate the biological neuron characteristics such as integration, threshold triggering, output generation, and refractory period, using floating body MOSFET. The neuron circuit sends feedback signal to the synaptic transistor for long-term memory.

The Relationship Between Stability and Gain Band-width Product in the Switching Regulator (스위칭 레귤레이터의 안전성과 이득대역폭적과의 관계)

  • Kim, H.J.;Lee, I.H.
    • Proceedings of the KIEE Conference
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    • 1988.11a
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    • pp.399-402
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    • 1988
  • In this paper, the relationship between stability and gain band-width product (GB) is clear ed by evaluating the feedback gain in the buck-boost switching regulator. Especially, considering the effect of the right-half-plane pole on the stability, we found available region of GB on the stability with the one pole compensation for the feedback circuit.

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Integrated driver with optical compensation for improved uniformity of emissive displays

  • Maeyaert, Stefaan;Bakeroot, Benoit;Doutreloigne, Jan;Monte, Ann;Bauwens, Pieter;Calster, Andre Van
    • 한국정보디스플레이학회:학술대회논문집
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    • 2008.10a
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    • pp.692-695
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    • 2008
  • Large area emissive displays have problems with nonuniform pixel characteristics and their individual ageing. A pixel integrated driver with pixel based optical feedback is presented to solve these problems. Photodetectors, optical feedback circuit and data handling capabilities are integrated in a high voltage CMOS technology.

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A sub-optimal controller design for constant-frequency series resonant converter with buck type pre-regulator (벅형 프리레귤레이터를 가진 일정주파수 직렬공진변환기를 위한 새로운 준최적제어기 설계)

  • 안희욱;고정호;윤명중
    • 제어로봇시스템학회:학술대회논문집
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    • 1990.10a
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    • pp.96-100
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    • 1990
  • Dynamic modelling and controller design technique for constant-frequency series resonant converter with buck type preregulator are mainly described in this paper. An equivalent circuit model is derived and a state equation is developed from this model. To improve the dynamic performance, a negative feedback of inductor current is added to the proportional and integral control of output voltage. Furthermore, an optimization technique with prescribed eigenvalue region is applied to the determination of feedback gains. With the presented design method, much better dynamic performance can be obtained.

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Study on Sound Transmission through a Panel including Structural Vibration (구조 진동을 고려한 평판 구조물 음향 투과 특성 연구)

  • Chang, Woo-Suk;Kim, Won-Cheol
    • Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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    • 2011.10a
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    • pp.811-816
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    • 2011
  • This study includes investigation on sound transmission phenomena through a structural panel including structural vibration and feedback control methodology to minimize the transmission. Focus is placed on finding the relation between vibration pattern and sound transmission, and on finding optimal sensor and actuator location. A simple analog feedback control circuit is designed and implemented to verify the approach.

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A Study on the Fabrication of the Low Noise Amplifier Using a Series Feedback Method (직렬 피드백 기법을 이용한 저잡음 증폭기의 구현에 관한 연구)

  • 김동일;유치환;전중성;정세모
    • Journal of the Korean Institute of Navigation
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    • v.25 no.1
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    • pp.53-60
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    • 2001
  • This paper presents the fabrication of the LNA which is operating at 2.13 ~ 2.16 GHz for IMT-2000 front-end receiver using series feedback and resistive decoupling circuit. Series feedback added to the source lead of a GaAs FET keeps the low noise characteristics and drops the input reflection coefficient of a low noise amplifier simultaneously. Also, it increases the stability of the LNA. Resistive decoupling circuit is suitable for input stage matching because a signal at low frequency is dissipated by a resistor in the matching network. The amplifier consists of GaAs FET ATF-10136 for low noise stage and VNA-25 which is internally matched MMIC for high gain stage. The amplifier is fabricated with both the RF circuits and self bias circuit on the Teflon substrate with 3.5 permittivity. The measured results of the LNA which is fabricated using the above design technique are presented more than 30 dB in gain, PldB 17 dB and less than 0.7 dB in noise figure, 1.5 in inputㆍoutput SWR(Standing Wave Ratio).

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Reducing the Effects of Noise Light in an Wireless Optical Communication Using Optoelectronic Feedback (무선 광통신에서 광전 궤환을 이용한 잡음 광의 영향 감소)

  • Hwang, Da-Hyun;Lee, Seong-Ho
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.21 no.10
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    • pp.1136-1142
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    • 2010
  • In this paper, we reduced the optical noise interference using the ASK modulation with optoelectronic feedback in a wireless optical system in which a lighting LED is used as a light source. The carrier frequency of 70 kHz was generated internally by the oscillation in the optoelectronic feedback circuit, and the output light was ASK modulated at a data rate of 9.6 kbps by opening and shortening the feedback loop with the input signal. In an environment with adjacent noise lights, the ASK modulation with optoelectronic feedback improved the signal to noise ratio by about 25 dB.

Integrated Current-Mode DC-DC Buck Converter with Low-Power Control Circuit

  • Jeong, Hye-Im;Lee, Chan-Soo;Kim, Nam-Soo
    • Transactions on Electrical and Electronic Materials
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    • v.14 no.5
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    • pp.235-241
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    • 2013
  • A low power CMOS control circuit is applied in an integrated DC-DC buck converter. The integrated converter is composed of a feedback control circuit and power block with 0.35 ${\mu}m$ CMOS process. A current-sensing circuit is integrated with the sense-FET method in the control circuit. In the current-sensing circuit, a current-mirror is used for a voltage follower in order to reduce power consumption with a smaller chip-size. The N-channel MOS acts as a switching device in the current-sensing circuit where the sensing FET is in parallel with the power MOSFET. The amplifier and comparator are designed to obtain a high gain and a fast transient time. The converter offers well-controlled output and accurately sensed inductor current. Simulation work shows that the current-sensing circuit is operated with an accuracy of higher than 90% and the transient time of the error amplifier is controlled within $75{\mu}sec$. The sensing current is in the range of a few hundred ${\mu}A$ at a frequency of 0.6~2 MHz and an input voltage of 3~5 V. The output voltage is obtained as expected with the ripple ratio within 1%.