• Journal of KIISE:Computer Systems and Theory
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• v.29 no.2
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• pp.75-86
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• 2002

The selection of the optimal checkpointing interval has been a very critical issue to implement a checkpointing recovery scheme for the fault tolerant distributed system. This paper presents a new scheme that allows a process to select the proper checkpointing interval dynamically. A process in the system evaluates the cost of checkpointing and possible rollback for each checkpointing interval and selects the proper time interval for the next checkpointing Unlike the other scheme, the overhead incurred by both of the checkpointing and rollback activities are considered for the cost evaluation and current communication pattern is reflected in the selection of the checkpointing interval. Moreover, the proposed scheme requires no extra message communication for the checkpointing interval selection and can easily be incorporated into the existing checkpointing coordination schemes.

• The KIPS Transactions:PartA
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• v.9A no.3
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• pp.333-340
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• 2002

Embedding is a mapping an interconnection network G to another interconnection network H. If a network G can be embedded to another network H, algorithms developed on G can be simulated on H. In this paper, we first propose a method to embed between Hierarchical Cubic Network HCN(n, n) and Hierarchical Folded-hypercube Network HFN(n, n). HCN(n, n) and HFN(n, n) are graph topologies having desirable properties of hypercube while improving the network cost, defined as degree${\times}$diameter, of Hypercube. We prove that HCN(n, n) can be embedded into HFN(n, n) with dilation 3 and congestion 2, and the average dilation is less than 2. HFN(n, n) can be embedded into HCN(n, n) with dilation 0 (n), but the average dilation is less than 2. Finally, we analyze the fault tolerance of HCN(n, n) and prove that HCN(n, n) is maximally fault tolerant.

• Journal of the Optical Society of Korea
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• v.13 no.1
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• pp.98-106
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• 2009

This paper proposes an optical wireless transfer agent method which realizes the continuous and swift data transfer of optical wireless terminals in optical wireless networks. The unguided wireless channel generally shows frequent link disconnections and propagation delays due to weak wireless links. Specially speaking, optical wireless channels have more vulnerable links and roaming propagation delays relative to the weakness of the previous RF channels due to their low signal connectivity and small geographic coverage. Conventional optical wireless network protocols did not consider any fault models about physical link faults. Consequently, they have shown data transfer inefficiency for both data link control and physical wireless link control. To overcome these optical wireless environmental problems, this paper suggests a new wireless access point (or base station) agent system, which provides wireless or mobile clients with previous link layer protocols compensated.

• Proceedings of the Korea Institutes of Information Security and Cryptology Conference
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• 2003.12a
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• pp.141-145
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• 2003

We propose the model of Software Rejuvenation methodology, which is applicable for survivability. Software rejuvenation is a proactive fault management technique and being used in fault tolerant systems as a cost effective technique for dealing with software faults. Survivability focuses on delivery of essential services and preservation of essential assets, even systems are penetrated and compromised. Thus, our objective is to detect the intrusions in a real time and survive in face of such attacks. As we deterrent against an attack in a system level, the Intrusion tolerance could be maximized at the target environment. We address the optimal time to execute ad hoc software rejuvenation and we compute it by using the semi Markov process. This is one way that could be really frustrated and deterred the attacks, as the attacker can't make their progress. This Software Rejuvenation method can be very effective under the assumption of unknown attacks. In this paper, we compute the optimum time to perform an ad hoc Software Rejuvenation through intrusions.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.32 no.4
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• pp.101-110
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• 2004

Flight and Qualification Models of Single Board Computer (SBC), called On-Board Computer (OBC), for HAUSAT-l picosatellite, which is scheduled to launch on September, 2004 by Russian "Dnepr" launch vehicle, have been developed. The OBC of HAUSAT-1 has been designed with some improved features compared to other picosatellites. A multifunctional controller and up-to-date SPI (Serial Peripheral Interface) and 1-Wire interface are implemented to simplify the harness routing and to minimize the mass and size of OBC. The improved fault-tolerant architecture design methodology is incorporated in the HAUSAT-1 OBC to protect against space radiation environment. The functions of the OBC were fully tested and verified by the Electrical Test Bed (ETB) model. This paper is also addressing the environmental test results, such as random vibration and thermal vacuum tests.

• Journal of KIISE:Computer Systems and Theory
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• v.31 no.10
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• pp.553-561
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• 2004

Leader election is an important problem in developing fault-tolerant distributed systems. As a classic solution for leader election, there is Garcia-Molina's Bully Algorithm based on time-outs in synchronous systems. In this paper, we re-write the Bully Algorithm to use a failure detector instead of explicit time-outs. We show that this algorithm is more efficient than the Garcia-Molina's one in terms of the processing time. That is because the Bully_FD uses FD to know whether the process is up or down so fast and it speed up its execution time. Especially, where many processes are connected in the system and crash and recovery of processes are frequent, the Bully_FD algorithm is much more efficient than the classical Bully algorithm in terms of the processing time.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.8 no.10
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• pp.3361-3377
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• 2014

Synchronous computing models provided by real-time synchrony protocols, such as TTA [1] and PALS [2], greatly simplify the design, implementation, and verification of real-time distributed systems. However, their application to real systems has been limited since their assumptions on underlying systems are hard to satisfy. In particular, most previous real-time synchrony protocols hypothesize the existence of underlying fault tolerant real-time networks. This, however, might not be true in most soft real-time applications. In this paper, we propose a practical approach to a synchrony protocol, called Quality-Aware PALS (qPALS), which provides the benefits of a synchronous computing model in environments where no fault-tolerant real-time network is available. qPALS supports two flexible global synchronization protocols: one tailored for the performance and the other for the correctness of synchronization. Hence, applications can make a negotiation flexibly between performance and correctness. In qPALS, the Quality-of-Service (QoS) on synchronization and consistency is specified in a probabilistic manner, and the specified QoS is supported under dynamic and unpredictable network environments via a control-theoretic approach. Our simulation results show that qPALS supports highly reliable synchronization for critical events while still supporting the efficiency and performance even when the underlying network is not stable.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1998.06a
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• pp.515-520
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• 1998

In this paper, we propose a new fault tolerant architecture for high availability systems, where for module internal operations both processor modules perform the same tasks at the same time independently of each other while for module external operations both processor modules act actively. That is, operations of synchronization between dual processor modules except clock synchronization are requested only when module external operations are executed. The architecture can not only improve system availability by reducing system reintegration time but also reduce performance degradation problem due to frequent synchronization between dual processor modules. The clock unit consists of a clock generator and a clock synchronization circuit. This supplies a stable clock signal under clock unit disorder of any processor module or rapid clock signal variation. And this architecture achieves system availability and data credibility by designing as symmetrical form.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.12 no.4
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• pp.1889-1896
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• 2011

There has been a lot of researches to develop techniques that provide redundant paths, there by making Multistage Interconnection Networks(MINs) fault tolerant. So far, the redundant paths in MINs have been realized by adding additional hardware such as extra stages or duplicated data links. This paper presents a new MIN topology called Hierarchical MIN. The proposed MIN is constructed with 2.5N-4 switching elements, which are much fewer than that of the classical MINs. Even though there are fewer hardware than the classical MINs, the HMIN possesses the property of full access and also provides alternative paths for the fault tolerant. Furthermore, since there is the short cut in HMIN for the localized communication, it takes advantage of exploiting the locality of reference in multiprocessor systems. Its performance under varying degrees of localized communication is analysed and simulated.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.11
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• pp.50-55
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• 2008

As more DSP functionalities are integrated into an embedded mobile device, power consumption and device reliability have emerged as crucial issues. As the complexity of mobile embedded designs increases very rapidly, verifying the functionality of the mobile devices has become extremely difficult. Therefore, designs with error (fault) tolerance are often required since these capabilities will enable the design to operate properly even with some existence of errors. However, designs with fault tolerance may suffer from significant power overhead since fault tolerance is often achieved by resource replication. In this paper, we propose a low power and fault tolerant MAC (multiply-and-accumulate) design. The proposed MAC design is based on multiple barrel shifters since MAC designs with barrel-shifters and adders are known to be excellent in terms of power consumption.