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A Design of Low Power MAC Operator with Fault Tolerance  

Jung, Han-Sam (Dept. of Electronics, Computer & Communication Engineering, Hanyang University)
Ku, Sung-Kwan (OPTICS & IMAGING DIVISION, Samsung Techwin)
Chung, Ki-Seok (Dept. of Electronics, Computer & Communication Engineering, Hanyang University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.45, no.11, 2008 , pp. 50-55 More about this Journal
Abstract
As more DSP functionalities are integrated into an embedded mobile device, power consumption and device reliability have emerged as crucial issues. As the complexity of mobile embedded designs increases very rapidly, verifying the functionality of the mobile devices has become extremely difficult. Therefore, designs with error (fault) tolerance are often required since these capabilities will enable the design to operate properly even with some existence of errors. However, designs with fault tolerance may suffer from significant power overhead since fault tolerance is often achieved by resource replication. In this paper, we propose a low power and fault tolerant MAC (multiply-and-accumulate) design. The proposed MAC design is based on multiple barrel shifters since MAC designs with barrel-shifters and adders are known to be excellent in terms of power consumption.
Keywords
Fault Tolerance; Low Power; MAC; Barrel Shifter;
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  • Reference
1 D. K. Pradhan, "Fault-Tolerant Computing Theory and Techniques", Prentice Hall, pp. 417-466, 1986
2 R. D. Schlichting and F. B. Schneider, "Fail-stop processors: an approach to designing fault- tolerant computing systems", ACM Transactions on Computing Systems, 1: 222-238, 1983   DOI
3 Barry W. Johnson, "Design and Analysis of Fault Tolerant Digital Systems", Addison Wesley, pp. 169-262, 1989
4 Hassan B. Diab and Albert Y. Zomaya, "Dependable Computing Systems Paradigms, Performance Issues, And Applications", WILEY- Interscience, pp. 213-241, 2005
5 J. C. Laprie, J. Arlat, C. Beounes, and K. Kanoun, "Definition and analysis of hardware- and-software fault-tolerant architectures", IEEE Computer, 23: 39-51, 1990
6 M. Potkonajak, M. Srivastava, and A. Chandrakasan, "Multiple Constant Multiplications: Efficient and Versatile Framework and Algorithms for Exploring Common Subexpression Eliminiation", IEEE Trans. on CAD of Integrated Circuits and Systems, Vol. 15, No. 2, pp. 151-165, February 1996   DOI   ScienceOn
7 Young-Geun Lee, Joo-Yul Park, and Ki-Seok Chung, "Design of Low Power MAC Operator with Dual Precision Mode", 13th IEEE conference on RTCSA, pp. 309-315, DAEGU, KOREA, August 2007
8 A. G. Dempster and M. D. Macleod, "Constant integer multiplication using minimum adders", Proc. Inst. Elec. Eng. Circuits and systems, vol. 141, no. 5, pp. 407-413, October 1994
9 Chien-Chung Chua, Bah-Hwee Gwee and Joseph S. Chang, "A low-voltage micropower asynchronous multiplier for a multiplierless FIR filter", In Proc. of the 2003 Int'l Symposium on Circuits and Systems, pp. 381-384, May 2003