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http://dx.doi.org/10.5762/KAIS.2011.12.4.1889

Biased Multistage Inter connection Network in Multiprocessor System  

Choi, Chang-Hoon (School of Computer Information, Kyungpook National University)
Publication Information
Journal of the Korea Academia-Industrial cooperation Society / v.12, no.4, 2011 , pp. 1889-1896 More about this Journal
Abstract
There has been a lot of researches to develop techniques that provide redundant paths, there by making Multistage Interconnection Networks(MINs) fault tolerant. So far, the redundant paths in MINs have been realized by adding additional hardware such as extra stages or duplicated data links. This paper presents a new MIN topology called Hierarchical MIN. The proposed MIN is constructed with 2.5N-4 switching elements, which are much fewer than that of the classical MINs. Even though there are fewer hardware than the classical MINs, the HMIN possesses the property of full access and also provides alternative paths for the fault tolerant. Furthermore, since there is the short cut in HMIN for the localized communication, it takes advantage of exploiting the locality of reference in multiprocessor systems. Its performance under varying degrees of localized communication is analysed and simulated.
Keywords
Interconnection Networks; Multistage Networks; Multiprocessor Systems;
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