• ETRI Journal
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• v.33 no.1
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• pp.50-59
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• 2011

In the current very deep submicron technology era, fault tolerant mechanisms perform an essential function to cope with the effects of soft errors. To evaluate the effectiveness of the fault tolerant mechanism, reliability engineers use simulated fault injections using either saboteur modules or mutants in the simulation model. However, the two methods suffer from both inefficiency in the simulation mechanism and difficulties with the experimental setups. To overcome these inefficiencies, we propose the Verilog-based simulated fault injection (VFI) technique. VFI has the following advantages. First, modification of the design model is unnecessary. Second, the fault injection simulation procedure is simple and efficient. Third, various types of fault injection experiments can be performed. To evaluate the effectiveness of the proposed methodology, we developed a VFI environment using the ICARUS Verilog Simulator. From the experimental results, we were able to qualitatively evaluate the reliability of the target simulation models and to assess the effectiveness of the employed fault-tolerance mechanisms.

• ETRI Journal
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• v.39 no.4
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• pp.605-613
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• 2017

Simulated fault injection (SFI) is widely used to assess the effectiveness of fault tolerance mechanisms in safety-critical embedded systems (SCESs) because of its advantages such as controllability and observability. However, the long test time of SFI due to the large number of test cases and the complex simulation models of modern SCESs has been identified as a limiting factor. We present a method that can accelerate an SFI tool using a checkpoint forwarding (CF) technique. To evaluate the performance of CF-based SFI (CF-SFI), we have developed a CF mechanism using Verilog fault-injection tools and two systems under test (SUT): a single-core-based co-simulation model and a triple modular redundant co-simulation model. Both systems use the Verilog simulation model of the OpenRISC 1200 processor and can execute the embedded benchmarks from MiBench. We investigate the effectiveness of the CF mechanism and evaluate the two SUTs by measuring the test time as well as the failure rates. Compared to the SFI with no CF mechanism, the proposed CF-SFI approach reduces the test time of the two SUTs by 29%-45%.

• Journal of the Korea Society for Simulation
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• v.9 no.2
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• pp.51-61
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• 2000

In recent years, significant advances in computers and communication technologies have made multimedia services feasible. As a result, various queueing models and cost models on architecture and data placement for multimedia server have been proposed. However, most of these models do not evaluate dependability of systems. In the design phase of a system, simulation is an important experimental means for performance and dependability analysis. Fault injection simulation has been used in evaluation of dependability metric. In this paper, we develop fault injection simulation model to analyze dependability of parallel video servers. In addition, we evaluate reliability and MTTF(Mean Time To Failure) of systems by using the simulator.

• Journal of information and communication convergence engineering
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• v.19 no.3
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• pp.175-179
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• 2021

Enhancing the reliability of the system is important for recent system-on-chip (SoC) designs. This importance has led to studies on fault diagnosis and tolerance. Fault-injection (FI) techniques are widely used to measure the fault-tolerance capabilities of resilient systems. FI techniques suffer from limitations in relation to environmental conditions and system features. Moreover, a hardware-based FI can cause permanent damage to the target system, because the actual circuit cannot be restored. Accordingly, we propose a simulation-based FI framework based on the Verilog Procedural Interface for measuring the failure rates of SoCs caused by soft errors. We execute five benchmark programs using an ARM Cortex M0 processor and inject soft errors using the proposed framework. The experiment has a 95% confidence level with a ±2.53% error, and confirms the reliability and feasibility of using proposed framework for fault analysis in SoCs.

• ETRI Journal
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• v.33 no.3
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• pp.434-442
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• 2011

This paper presents a practical differential fault analysis method for the faulty Advanced Encryption Standard (AES) with a reduced round by means of a semi-invasive fault injection. To verify our proposal, we implement the AES software on the ATmega128 microcontroller as recommended in the standard document FIPS 197. We reduce the number of rounds using a laser beam injection in the experiment. To deduce the initial round key, we perform an exhaustive search for possible key bytes associated with faulty ciphertexts. Based on the simulation result, our proposal extracts the AES 128-bit secret key in less than 10 hours with 10 pairs of plaintext and faulty ciphertext.

• Journal of Advanced Navigation Technology
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• v.14 no.2
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• pp.233-238
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• 2010

In this paper, we applied the forward and backward error recovery techniques to a reduced instruction set computer (risc) processor to develop two fault-tolerant processors, namely, fetch redundant risc (FRR) processor and a redundancy execute risc (RER) processor. To evaluate the fault-tolerance capability of three target processors, we developed the base risc processor, FRR processor, and RER processor in SystemC hardware description language. We performed fault injection experiment using the three SystemC processor models and the SystemC-based simulation fault injection technique. From the experiments, for the 1-bit transient fault, the failure rate of the FRR, RER, and base risc processor were 1%, 2.8%, and 8.9%, respectively. For the 1-bit permanent fault, the failure rate of the FRR, RER, and base risc processor were 4.3%, 6.5%, and 41%, respectively. As a result, for 1-bit fault, we found that the FRR processor is more reliable among three processors.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.23 no.3
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• pp.371-381
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• 2013

An encryption algorithm is executed to supply data confidentiality using a secret key which is embedded in a crypto device. However, the fault injection attack has been developed to extract the secret key by injecting errors during the encryption processes. Especially, an attacker can find the secret key of block cipher ARIA using about 33 faulty outputs. In this paper, we proposed a countermeasure resistant to the these fault injection attacks by checking the difference value between input and output informations. Using computer simulation, we also verified that the proposed countermeasure has excellent fault detection rate and negligible computational overhead.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.22 no.5
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• pp.1009-1017
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• 2012

The fault injection attack has been developed to extract the secret key which is embedded in a crypto module by injecting errors during the encryption process. Especially, an attacker can find master key of AES using injection of just one byte. In this paper, we proposed a countermeasure resistant to the these fault attacks by checking the differences between input and output. Using computer simulation, we also verified that the proposed AES implementation resistant to fault attack shows better fault detection ratio than previous other methods and has small computational overheads.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.28 no.5
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• pp.1071-1078
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• 2018

Recently, a family of lightweight block ciphers CHAM that has effective performance on resource-constrained devices is proposed. The CHAM uses a stateless-on-the-fly key schedule method which can reduce the key storage areas. Furthermore, the core design of CHAM is based on ARX(Addition, Rotation and XOR) operations which can enhance the computational performance. Nevertheless, we point out that the CHAM algorithm may be vulnerable to the fault injection attack which can reveal 4 round keys and derive the secret key from them. As a simulation result, the proposed fault injection attack can extract the secret key of CHAM-128/128 block cipher using about 24 correct-faulty cipher text pairs.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.28 no.3
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• pp.551-561
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• 2018

As the computational technology using quantum computing has been developed, several threats on cryptographic systems are recently increasing. Therefore, many researches on post-quantum cryptosystems which can withstand the analysis attacks using quantum computers are actively underway. Nevertheless, the lattice-based NTRU system, one of the post-quantum cryptosystems, is pointed out that it may be vulnerable to the fault injection attack which uses the weakness of implementation of NTRU. In this paper, we investigate the fault injection attacks and their previous countermeasures on the NTRU signature system and propose a secure and efficient countermeasure to defeat it. As a simulation result, the proposed countermeasure has high fault detection ratio and low implementation costs.