• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.61 no.11
• /
• pp.1752-1757
• /
• 2012

With the development in industry, power demand has increased rapidly. As consumption of power has increased, Demand for new power line and electric capacity has risen. However, in the event of fault, problems occur in extending the range of fault coverage and increasing fault current. In these reasons, protection devise is recognized as the prevention of an accident and fault current. This paper dealt with minimizing fault propagation and limiting fault current by adjusting fault current limiter (FCL) with fast interrupter. At this point, we compared and analyzed characteristics between non-inductive resistance and fault current which is limited by superconducting units. In normal state of the power system, power was supplied to the load, but when fault occurred, the interrupter was operated as CT which detected the over-current. Its operation made the limitation of fault current through a FCL. We concluded that the limiter using superconducting units was more efficient with the increase of power voltage. Superconducting fault current limiter with the fast interrupter prevented the spread of a fault, and improved reliability of power system.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.19 no.8
• /
• pp.37-43
• /
• 2018

A developer solves problems with isolating failures if faults are detected when inspecting missiles using the missile assembly test set (MATS) and then resumes the testing. In order to identify faults, it is necessary to analyze the data coming from the equipment, but the information received may not be sufficient, depending on the inspection environment. In this case, the developer repeats the test until the problem is reproduced or checks the performance of each piece of equipment that is related to the fault. When this task is added, schedule management becomes problematic, and development costs rise. To solve this problem, we need to design a MATS in a systematic way to increase fault coverage while satisfying the required reliability. By designing the necessary processes for each procedure, it is possible to reduce the fault identification time when a fault is detected during operations. But it is not possible to guarantee 100% fault coverage, so we provide another method by comparing costs and effects. This paper describes a development method to enhance the reliability of the missile assembly test set; it describes the expected effects when it is adapted, and describes the limitations of this method.

• Proceedings of the IEEK Conference
• /
• 1999.06a
• /
• pp.397-400
• /
• 1999

As the result of enhancement of CAD, Design Automation and manufacturing technology, it's on the increasing complexity, integration ratio, data signals, and pin count to IC chips. This brings about difficulties of testing, and incresing test time. Now One of the most cost-consuming procedure as integration ratio increases is the testing step. In this paper, we propose a new method, “Efficient TP(test point) assignment algorithm” using “input grouping”, This is helpful method to reducing test length without losing fault coverage. Experimental results show that proposed method reduces test length remarkably and doesn't miss fault coverage, with low hardware overhead Increasing.

• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.35C no.3
• /
• pp.1-15
• /
• 1998

In this paper, we propose a partial scan test method which can be applied to large VLSI designs. In this method, it is not necessary to hold neither scanned nor unscanned flip-flops during scan in, test application,or scan out. This test method requires almost identical design for testability modification and test wave form when compared to the full scan test method, and the method is applicable to large VLSI chips. The well known FAN algorithm has been modified to devise to sequential ATPG algorithm which is effective for the proposed test method. In addition, a partial scan algorithm which is effective for the proposed test method. In addition, a partial algorithm determined a maximal set of flip-flops which gives high fault coverage when they are unselected. The experimental resutls show that the proposed method allow as large as 20% flip-flops to remain unscanned without much decrease in the full scan fault coverage.

• Journal of the Semiconductor & Display Technology
• /
• v.22 no.1
• /
• pp.49-53
• /
• 2023

In this paper, we propose an antirandom pattern-based test method considering power consumption to compensate for the problem that the fault coverage through random test decreases or the test time increases significantly when the DUT circuit structure is complex or large. In the proposed method, a group unit test pattern generation process and rearrangement process are added to improve the problems of long calculation time and high-power consumption, which are disadvantages of the previous antirandom test.

• Proceedings of the Korean Nuclear Society Conference
• /
• 2003.05a
• /
• pp.90-90
• /
• 2003

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.33A no.3
• /
• pp.176-186
• /
• 1996

As the density of VLSI increases, the conventional logic testing is not sufficient to completely detect the new faults generated in design and fabrication processing. Recently, IDDQ testing becomes very attractive since it can overcome the limitations of logic testing. In this paper, G-ATPG (gyeongsang automatic test pattern genrator) is designed which is able to be adapted to IDDQ testing for combinational CMOS VLSI. In G-ATPG, stuck-at, transistor stuck-on, GOS (gate oxide short)or bridging faults which can occur within priitive gate or XOR is modelled to primitive fault patterns and the concept of a fault-sensitizing gate is used to simulate only gates that need to sensitize the faulty gate because IDDQ test does not require the process of fault propagation. Primitive fault patterns are graded to reduce CPU time for the gates in a circuit whenever a test pattern is generated. the simulation results in bench mark circuits show that CPU time and fault coverage are enhanced more than the conventional ATPG using IDDQ test.

• ETRI Journal
• /
• v.30 no.4
• /
• pp.546-554
• /
• 2008

Phase-locked loops (PLLs) are among the most important mixed-signal building blocks of modern communication and control circuits, where they are used for frequency and phase synchronization, modulation, and demodulation as well as frequency synthesis. The growing popularity of PLLs has increased the need to test these devices during prototyping and production. The problem of distinguishing and classifying the responses of analog integrated circuits containing catastrophic faults has aroused recent interest. This is because most analog and mixed signal circuits are tested by their functionality, which is both time consuming and expensive. The problem is made more difficult when parametric variations are taken into account. Hence, statistical methods and techniques can be employed to automate fault classification. As a possible solution, we use the back propagation neural network (BPNN) to classify the faults in the designed charge-pump PLL. In order to classify the faults, the BPNN was trained with various training algorithms and their performance for the test structure was analyzed. The proposed method of fault classification gave fault coverage of 99.58%.

• International Journal of Reliability and Applications
• /
• v.7 no.2
• /
• pp.155-166
• /
• 2006

Many software reliability growth models (SRGMs) based on nonhomogeneous Poisson process (NHPP) have been developed and applied in practice. NHPP SRGMs are characterized by their mean value functions. Mean value functions are usually derived from differential equations representing the fault detection/removal process during testing. In this paper such differential equations are regarded as frameworks for generating mean value functions. Currently available frameworks are theoretically discussed with respect to capability of representing the fault detection/removal process. Then two general frameworks are proposed.

• ETRI Journal
• /
• v.31 no.2
• /
• pp.209-214
• /
• 2009

In this paper, we propose a novel test methodology for the detection of catastrophic and parametric faults present in analog very large scale integration circuits. An automatic test pattern generation algorithm is proposed to generate piece-wise linear (PWL) stimulus using wavelets and a genetic algorithm. The PWL stimulus generated by the test algorithm is used as a test stimulus to the circuit under test. Faults are injected to the circuit under test and the wavelet coefficients obtained from the output response of the circuit. These coefficients are used to train the neural network for fault detection. The proposed method is validated with two IEEE benchmark circuits, namely, an operational amplifier and a state variable filter. This method gives 100% fault coverage for both catastrophic and parametric faults in these circuits.