• Title/Summary/Keyword: Fast Settling

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Mechanism Design of Optical Pickup Actuator for Fast Access of Optical Disk Drive (광디스크 드라이브의 고속 액세스를 위한 광픽업 액추에이터 메커니즘 설계)

  • 박준혁;이상헌;백윤수
    • Journal of the Korean Society for Precision Engineering
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    • v.19 no.12
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    • pp.109-119
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    • 2002
  • In this paper, mechanism design of optical pickup actuator for fast access is proposed. This actuator is composed of moving magnet type actuator and moving coil type actuator for tracking and fine motion, respectively. Moving magnet type tracking actuator is configurated by two permanent magnets and four air-core solenoids. Additional damper by induced current in tracking actuator can reduce the transient vibration between the coarse seeking servo and fine seeking servo. Variable stiffness can be acquired by applying current to air-core solenoid simply. This actuator can achieve fast access by these additional damper and stiffness. Performance of this actuator is predicted through the FEM, simulation and simple experiment. Settling time for transient vibration is reduced to 14.7% according to simulation result.

Characterization of Physical Properties of Turbid Flow in the Daecheong Reservoir Watershed dining Floods (홍수시 대청호 유역에 발생하는 탁수의 물리적 특성)

  • Chung, Se Woong;Lee, Heung Soo;Yoon, Sung Wan;Ye, Lyeong;Lee, Jun Ho;Choo, Chang Oh
    • Journal of Korean Society on Water Environment
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    • v.23 no.6
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    • pp.934-944
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    • 2007
  • Fine suspended solids (SS) induced into a reservoir after flood events play important ecological and water quality roles by presenting persistent turbidity and attenuating light. Thus the origin and physical features must be characterized to understand their transport processes and associated impacts, and for the establishment of watershed based prevention strategies. This study was aimed to characterize the physical properties of the SS sampled from Daecheong Reservoir and its upstream rivers during flood events. Extensive field and laboratory experiments were carried out to identify the turbidity-SS relationships, particle size distributions, settling velocity, and mineral compositions of the SS. Results showed that the turbidity-SS relationships are site-specific depending on the locations and flood events in the system. The turbidity measured within the reservoir was much greater than that measured in the upstream rivers for the same SS value. The effective diameters ($D_{50}$) in the rivers were in the range of $13.3{\sim}54.3{\mu}m$, while those in the reservoir were reduced to $2.5{\sim}14.0{\mu}m$ due to a fast settling of large particles in the rivers. The major minerals consisting of the SS were found to be Illite, Muscovite, Albite, and Quartz both in the rivers and reservoir. Their apparent settling velocities at various locations in the reservoir were in the range of 0.06~0.13 m/day. The research outcome provides a fundamental information for the fine suspended particles that cause persistent turbidity in the reservoir, and can be used as basic parameters for modeling study to search watershed based optimal control measures.

250 mV Supply Voltage Digital Low-Dropout Regulator Using Fast Current Tracking Scheme

  • Oh, Jae-Mun;Yang, Byung-Do;Kang, Hyeong-Ju;Kim, Yeong-Seuk;Choi, Ho-Yong;Jung, Woo-Sung
    • ETRI Journal
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    • v.37 no.5
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    • pp.961-971
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    • 2015
  • This paper proposes a 250 mV supply voltage digital low-dropout (LDO) regulator. The proposed LDO regulator reduces the supply voltage to 250 mV by implementing with all digital circuits in a$0.11{\mu}m$ CMOS process. The fast current tracking scheme achieves the fast settling time of the output voltage by eliminating the ringing problem. The over-voltage and under-voltage detection circuits decrease the overshoot and undershoot voltages by changing the switch array current rapidly. The switch bias circuit reduces the size of the current switch array to 1/3, which applies a forward body bias voltage at low supply voltage. The fabricated LDO regulator worked at 0.25 V to 1.2 V supply voltage. It achieved 250 mV supply voltage and 220 mV output voltage with 99.5% current efficiency and 8 mV ripple voltage at $20{\mu}A$ to $200{\mu}A$ load current.

Design of Fuzzy PI Controller for Piezo Actuator of Nano Stage (나노 스테이지용 압전 구동기의 퍼지 PI 제어기 설계)

  • Cho, Seong-Yeon;Chung, Chung-Choo
    • Proceedings of the KIEE Conference
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    • 2003.11c
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    • pp.629-632
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    • 2003
  • Piezo actuators are mainly used in precision position control system because of their high position resolution. Although there have been many approaches in open loop control of this, those method turn out to be not effective in precision control due to hysteresis and creep. To overcome the problems, closed loop PI control method is used in commercial products. However, it is very difficult to obtain fast response with conventional PI control although piezo actuator has fast response. In this paper, we propose a fuzzy PI control method with the proposed fuzzy PI controller, we obtains faster settling response over the conventional PI controller. We verify the effectiveness of the proposed method with experimental results.

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Phase Tracking Settling Time and BER Performance Evaluation in the Digital Retrodirective Array Antenna System (디지털 역지향성 배열 안테나 시스템에서 위상 추적 Settling 시간과 BER 성능 평가)

  • Kim, So-Ra;Lee, Seung Hwan;Shin, Dong Jin;Ryu, Heung-Gyoon
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.24 no.1
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    • pp.55-63
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    • 2013
  • Digital retrodirective antenna system is easy to modify and upgrade because it can control the phase information of the output signal toward opposite direction to input signal without a priori knowledge of the arrival direction. Due to this advantage, it is possible to do fast beam tracking. Especially, we need to design the digital PLL performance for the digital retrodirective array antenna system. So, in this paper the settling time of phase estimator and BER performance of retrodirective antenna system are investigated according to design of filter in digital PLL. When QAM signal is used for 1 Mbps with $30^{\circ}$ of phase delay, simulation results show that digital phase conjugation technique has better BER performance by about 1 dB than non-phase conjugation system when digital filter is stable. If not, the system can't estimate the exact phase because of oscillation of filter.

Folded-Cascode Operational Amplifier for $32{\times}32$ IRFPA Readout Integrated Circuit using the $0.35{\mu}m$ CMOS process ($0.35{\mu}m$ CMOS 공정을 이용한 $32{\times}32$ IRFPA ROIC용 Folded-Cascode Op-Amp 설계)

  • Kim, So-Hee;Lee, Hyo-Yeon;Jung, Jin-Woo;Kim, Jin-Su;Kang, Myung-Hoon;Park, Yong-Soo;Song, Han-Jung;Jeon, Min-Hyun
    • Proceedings of the IEEK Conference
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    • 2007.07a
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    • pp.341-342
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    • 2007
  • The IRFPA (InfraRed Focal Plane Array) ROIC (ReadOut Integrated Circuit) was designed in folded-cascode Op-Amp using $0.35{\mu}m$ CMOS technology. As the folded-cascode has high open-loop voltage gain and fast settling time, that used in many analog circuit designs. In this paper, folded-cascode Op-Amp for ROIC of the $32{\times}32$ IRFPA has been designed. HSPICE simulation results are unit gain bandwidth of 13.0MHz, 90.6 dB open loop gain, 8 V/${\mu}m$ slew rate, 600 ns settling time and $66^{\circ}$ phase margin.

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PSO based tuning of PID controller for coupled tank system

  • Lee, Yun-Hyung;Ryu, Ki-Tak;Hur, Jae-Jung;So, Myung-Ok
    • Journal of Advanced Marine Engineering and Technology
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    • v.38 no.10
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    • pp.1297-1302
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    • 2014
  • This paper presents modern optimization methods for determining the optimal parameters of proportional-integral-derivative (PID) controller for coupled tank systems. The main objective is to obtain a fast and stable control system for coupled tank systems by tuning of the PID controller using the Particle Swarm Optimization algorithm. The result is compared in terms of system transient characteristics in time domain. The obtained results using the Particle Swarm Optimization algorithm are also compared to conventional PID tuning method like the Ziegler-Nichols tuning method, the Cohen-Coon method and IMC (Internal Model Control). The simulation results have been simulated by MATLAB and show that tuning the PID controller using the Particle Swarm Optimization (PSO) algorithm provides a fast and stable control system with low overshoot, fast rise time and settling time.

Fast Transient Response Techniques for PWM Buck Converter (PWM 방식 벅 컨버터의 빠른 과도응답 기술)

  • Seok, Jinmin;Suh, Jung-Duk;Kong, Bai-Sun
    • Journal of IKEEE
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    • v.20 no.1
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    • pp.103-106
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    • 2016
  • PWM buck converters usually use a type-III error amplifier. Since this amplifier has a big capacitor with slow slew rate, they can generate an unintended large overshoot/undershoot at the output when a large load current change occurs. They can also respond slowly by varying the reference voltage. In order to increase battery lifetime, power supplies require a various range of load current and output voltage. PWM buck converter also should have a characteristic of both fast load response and reference tracking. This paper surveys a few recent techniques for reducing the settling time, and discusses their merits and limitations.

Characteristic Analysis of LDO Regulator According to Process Variation (공정변화에 따른 LDO 레귤레이터의 특성 분석)

  • Park, Won-Kyeong;Kim, Ji-Man;Heo, Yun-Seok;Park, Yong-Su;Song, Han-Jung
    • 전자공학회논문지 IE
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    • v.48 no.4
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    • pp.13-18
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    • 2011
  • In this paper, we have examined electrical characteristics of LDO regulator according to the process variation using a 1 ${\mu}m$ 20 V high voltage CMOS process. The electrical analysis of LDO regulator have been performed with three kind of SPICE parameter sets (Typ : typical, FF : fast, SS : slow) by process variation which cause change of SPICE parameter such as threshold voltage and effective channel length of MOS devices. From simulation results, we confirmed that in case of SS type SPICE parameter set, the LDO regulator has 3.6 mV/V line regulation, 0.4 mV/mA load regulation and 0.86 ${\mu}s$ output voltage settling time. And in case of Typ type SPICE parameter set, the LDO regulatorhas 4.2 mV/V line regulation, 0.44 mV/mA load regulation and 0.62 ${\mu}s$ output voltage settling time. Finally, in the FF type SPICE parameter set, the LDO regulator has 7.0 mV/V line regulation, 0.56 mV/mA load regulation and 0.27 ${\mu}s$ output voltage settling time.

A 1.248 Gb/s - 2.918 Gb/s Low-Power Receiver for MIPI-DigRF M-PHY with a Fast Settling Fully Digital Frequency Detection Loop in 0.11 ㎛ CMOS

  • Kim, Sang-Yun;Lee, Juri;Park, Hyung-Gu;Pu, Young Gun;Lee, Jae Yong;Lee, Kang-Yoon
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.15 no.4
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    • pp.506-517
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    • 2015
  • This paper presents a 1.248 Gb/s - 2.918 Gb/s low-power receiver MIPI-DigRF M-PHY with a fully digital frequency detection loop. MIPI-DigRF M-PHY should be operated in a very short training time which is $0.01{\mu}s$ the for HS-G2B mode. Because of this short SYNC pattern, clock and data recovery (CDR) should have extremely fast locking time. Thus, the quarter rate CDR with a fully digital frequency detection loop is proposed to implement a fast phase tracking loop. Also, a low power CDR architecture, deserializer and voltage controlled oscillator (VCO) are proposed to meet the low power requirement of MIPI-DigRF M-PHY. This chip is fabricated using a $0.11{\mu}m$ CMOS process, and the die area is $600{\mu}m{\times}250{\mu}m$. The power consumption of the receiver is 16 mW from the supply voltage of 1.1 V. The measured lock time of the CDR is less than 20 ns. The measured rms and peak jitter are $35.24ps_{p-p}$ and $4.25ps_{rms}$ respectively for HS-G2 mode.