• Journal of the Korea Institute of Military Science and Technology
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• v.13 no.5
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• pp.775-784
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• 2010

In this paper we propose a design method of X band frequency hopping synthesizer in terms of phase noise and settling time with DDS driven PLL architecture, which has the advantages of high frequency resolution, fast settling time and small size. In addition, a noble method is proposed to remove the synthesizer output spurious signals due to superposition effect of DDS. The spurious signal which depend on its normalized frequency of DDS, can be dominant if they occur within the PLL loop bandwidth. We verify that the sources of that spurious signals are quasi-amplitude modulation and superposition effect, and suggest that such signals can be eliminated by intentionally creating frequency errors in the developed synthesizer.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.607-608
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• 2006

A CMOS phase-locked loop (PLL) which synthesizes frequencies between $6.336{\sim}8.976GHz$ in steps of 528MHz and settles in approximately 150ns using the 528MHz reference clock is presented. Frequency hopping between the bands in the each mode is critical point to design the PLL in multi-band orthogonal frequency division multiplexing (OFDM) because frequency switching between each band is less than 9.5ns. To achieve the fast loop settling, integer-N PLL that operates with the high reference frequency to meet the settling requirement is implemented. Two PLLs that operate at 9GHz and 528MHz is integrated and shows the band hopping lower than 1ns.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.8
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• pp.1543-1548
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• 2009

In this paper, a high speed code synchronization circuit is proposed. for fast code synchronization, matched filler method is used for initial code acquisition with two channel correlators. Particular frequency patterns of the limited number having the information about PN code start time are composed and transmitted repeatedly to increase the probability of accurate initial synchronization. And digital frequency synthesizer is proposed. And it's performance is analyzed theoretically. The analysis show that fast frequency hopping is possible in frequency hopping system that use digital frequency synthesizer.

• Journal of Korea Society of Digital Industry and Information Management
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• v.8 no.3
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• pp.65-74
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• 2012

A barcode is a representative means of cognition. It is either printed on the package of a product or attached to it as a sticker. It is used for the fast cognition of a product at a store. It is considerably cheap to make a barcode. Also, it is possible to read it fast by using a barcode reader. Because of such convenience provided by the barcode, a new system using the barcode as a means of settling payments like a currency or a credit card has been developed. However, due to its characteristics, it is easy to reduplicate, forge or falsify a barcode easily. Therefore, this study focuses on the case of applying the system using barcodes as a means of settling payments without providing solutions for the potential weaknesses. Also, this study suggests various points to consider regarding the creation of safe barcodes as one of the related measures, while providing various methods using additional means of certification other than the one of using barcodes in addition to the way of applying complexity with barcode numbers. Throughout this study, it will be possible to safely establish and operate the payment-settlement system using barcodes.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.25 no.12
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• pp.1251-1257
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• 2014

In this paper, a 6~13 GHz ultra high speed frequency synthesizer having minimum 30 kHz step size and minimum 500 ns frequency settling time is proposed. In order to obtain fast settling time, fine resolution, and good phase noise performance, wideband output frequencies were synthesized based on DDS(Direct Digital Synthesizer) and analog direct frequency synthesis technology. The phase noise performance of wideband frequency synthesizer was estimated by the superposition theory and its results were compared with measured ones. The measured frequency settling time was below 500 ns, phase noise was below -106 dBc @ 10 kHz at 13 GHz, and frequency accuracy was measured below ${\pm}2kHz$.

• Proceedings of the KIPE Conference
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• 1999.07a
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• pp.80-83
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• 1999

The windup phenomenon appears and results in performance degradation such as large overshoot, slow settling time when the integral-proportional (IP) controller output is saturated. An anti-windup IP controller is proposed to improve the control performance for the motor drives. The proposed algorithm is applied to the current control of a vector-controlled induction motor driven by a pulse width modulated(PWM) voltage-source inverter. The integral state is separately controlled corresponding to whether the IP controller output is saturated or not. The experimental results show that the current response has much improved performance such as little overshoot and fast settling time.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 1996.11a
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• pp.820-825
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• 1996

This paper is concerned with effective operating method of pneumatic on-off valves for improving position control accuracy, valve life-time and position settling time using modified pulse width modulation with dead-zone. The pneumatic system using on-off valves studied in this paper has advantage of simple construction and low cost compared with a system with servo-valves. The performance of proposed control system is investigated experimentally for the position control of a pneumatic cylinder using on-off valves. Experimental results show that the proposed algorithm for valve operation can be used to obtain fast and accurate position control and to prevent on-off valves from unnecessary switching.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.51 no.6
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• pp.252-257
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• 2002

We designed a neuro-fuzzy controller to improve some problems that are happened when the DC servo motor is controlled by a PID controller or a fuzzy logic controller. Our model proposed in this paper has the stable and accurate responses, and shortened settling time. To prove the capability of the neuro-fuzzy controller designed in this paper, the proposed controller is applied to the speed control of DC servo motor. The results showed that the proposed controller did not produce the overshoot, which happens when PID controller is used, and also it did not produce the steady state error when FLC is used. And also, it reduced the settling time about 10%. In addition, we could by aware that our model was only about 60% of the value of current peak of PID controller.

• Journal of Electrical Engineering and Technology
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• v.6 no.5
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• pp.658-665
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• 2011

In the present paper, a novel fast peak detector for single- or three-phase unsymmetrical voltage sags is proposed. The proposed detector is modified from a single-phase digital phase-locked loop based on a d-q transformation using an all-pass filter (APF). APF generates a virtual phase with $90^{\circ}$ phase delay. However, this virtual phase cannot reflect a sudden change of the grid voltage in the moment of voltage sag, which causes a peak value to be significantly distorted and to settle down slowly. Specifically, the settling time of the peak value is too long when voltage sag occurs around a zero crossing, such as phase $0^{\circ}$ and $180^{\circ}$. This paper describes the operating principle of the APF problem and proposes a modified all-pass filter (MAPF) to mitigate the inherent APF problem. In addition, a new fast peak detector using MAPF is proposed. The proposed detector is able to calculate a peak value within 0.5 ms, even when voltage sag occurs around zero crossing. The proposed fast peak detector is compared with the conventional detector using APF. Results show that the proposed detector has faster detection time in the whole phase range. Furthermore, the proposed fast peak detector can be effectively applied to unsymmetrical three-phase voltage sags. Simulation and experimental results verify the advantages of the proposed detector and MAPF.

• Journal of the Korean Vacuum Society
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• v.5 no.4
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• pp.284-291
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• 1996

We have implemented a fast pressure control system for the transport chamber of a high vacuum cluster tool for advance semiconductor fabrication and evaluated its performance. To overcome the typically slow response of mass flow controllers, the modified experimental method is used very effectively to optimize the pressure control procedure. We successfully obtained quite fast pressure control by adjusting the starting time and eht tuning constants by the Ziegler-Nichols method. In the transport pressure $10\times 10^{-5}$ torr, actual pressure control starts from 4 sec after an initial gas load of 2.1 sccm. As a result, optimum conditions for the tuning constants are the rise rate of 0.02 torr/sec, the lag time of 0.15 sec, and the sampling period of 0.5 sec. Then the settling time is about 9 sec within about $\pm$0.5% for the referenced value. This settling time is enhanced above 75 percents in comparison with conventional experimental method. To account for the experimental effects observed, a theoretical model was developed. This experimental result has a tendency to fit with the theoretical result of $\omega$=-1.0.