• Title/Summary/Keyword: Fast Settling

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A Study on the Generalization of the Manabe Standard Forms with the Genetic Algorithm

  • Kang, Hwan-Il;Jung, Yo-Won
    • 제어로봇시스템학회:학술대회논문집
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    • 1999.10a
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    • pp.116-120
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    • 1999
  • The step response of the Manabe standard form[1]has little overshoot and shows almost same waveforms regardless of the order of the characteristic polynomials. In some situations it is difficult to control the rise time and settling time simultaneously of the step response of the Manabe standard form. To control its rise time and settling time efficiently, we develop the generalization of the Manabe standard form: we try to find out the SRFS(Slow Rise time & Fast Settling time) form which has the slower rise time and faster settling time than those of the Manabe standard form. we also consider the other three forms: FRSS(Fast Rise time & Slow Settling time), SRFS(Slow Rise time & Fast Settling time) and SRSS(Slow Rise time & Slow Settling time) forms. In this paper, by using the genetic algorithm, we obtain all the coefficient of the four forms we mention above. Finally, we design a controller for a given plant so that the overall system has the performance that the rise time is faster, the settling time is slower than those of the Manabe standard form.

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A Study on the Manabe Standard Form Using the Evolutionary Strategy (진화전략을 이용한 Manabe 표준형에 관한 연구)

  • 강환일;정요원
    • The Transactions of the Korean Institute of Electrical Engineers D
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    • v.50 no.2
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    • pp.65-71
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    • 2001
  • The step response of the Manabe standard form[2] has little overshoot and show almost same waveforms regardless of the order of the characteristic polynomials. In some situations it is difficult to control the rise time and settling time simultaneously of the step response of the Manabe standard form To control its rise time and settling time efficiently, We develop the Manabe standard form: We try to find out the SRFS(Slow Rise time & Fast Setting time) form which has the slower rise time and faster settling time than those fo the Manabe standard form. We also consider the other three forms: FRSS(Fast Rise time & Slow Settling time), SRFS(Slow Rise time & Fast Settling time) and SRSS(Slow Rise time & Slow Settling time) forms. In this paper, by using the evolutionary strategy, we obtain all the coefficient of the four forms we mention above. Finally, we design a controller for a given plant so that the overall system has the performance that the rise time is faster, the settling time is faster than those of the Manabe standard form.

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A New Mode Switching Control for Fast Settling and High Precision Positioning (고속 세틀링과 고정밀 위치 제어를 위한 모드 변경 제어 기법)

  • Kim, Jung-Jae;Choi, Young-Man;Kim, Ki-Hyun;Gweon, Dae-Gab;Hong, Dong-Pyo
    • Journal of the Semiconductor & Display Technology
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    • v.5 no.4 s.17
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    • pp.1-4
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    • 2006
  • Recently, with rapid development of digital media like semiconductor and large flat panel display, the manufacturing equipment is required to have high precision over large travel range. Moreover it should have high product throughput. To achieve high product throughput, a controller should perform fast point-to-point motion and high precision positioning after settling in spite of external disturbances or residual vibrations. We proposed a new mode switching control algorithm with an application to dual stage for long range and high precision positioning. The proposed algorithm uses a proximate time-optimal servomechanism for the fast settling and a time-delay controller for the high precision positioning. Experimental results show that the proposed method enables smooth mode switching and improves the settling time and the precision accuracy after settling by over than 33% and 45%, respectively.

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Numerical analysis of flow and settling efficiency in a sedimentation basin (수치모의를 통한 침사지에서의 흐름 및 침사효율 해석)

  • Kim, Dae-Guen;Kim, Sung-Man;Park, Won-Cheol
    • Journal of Korean Society of Water and Wastewater
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    • v.24 no.6
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    • pp.713-722
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    • 2010
  • This paper has assessed the flow patterns and settling efficiency in the sedimentation basin using the particle tracking method of the CFD code and has reached the following conclusions: In the original design where no baffle is installed in the sedimentation basin, a large recirculating area where the flow stagnates is created in the right side of the sedimentation basin, with most of the particles moving to the left side of the sedimentation basin following the flow. This biased flow structure in the sedimentation basin reduces the residence time of particles and thereby undermines settling efficiency. The biased flow toward the left side of the sedimentation basin is alleviated by installing a baffle in the sedimentation basin, promptly reducing the fast flow of over 0.7 m/s in the inlet of the sedimentation basin to the rate below 0.2 m/s. In this paper's simulation conditions, if a one-sided baffle is to be installed in the sedimentation basin, placing it 15 meters away from the basin's inlet leads to the best settling efficiency; it has also been analyzed that installing a two-sided baffle-rather than a one-sided one-is a better option in terms of settling efficiency. The highest settling efficiency of 96.2% is achieved when the underwater length of the two-sided baffle is set at 8 meters.

Low-ripple coarse-fine digital low-dropout regulator without ringing in the transient state

  • Woo, Ki-Chan;Yang, Byung-Do
    • ETRI Journal
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    • v.42 no.5
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    • pp.790-798
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    • 2020
  • Herein, a low-ripple coarse-fine digital low-dropout regulator (D-LDO) without ringing in the transient state is proposed. Conventional D-LDO suffers from a ringing problem when settling the output voltage at a large load transition, which increases the settling time. The proposed D-LDO removes the ringing and reduces the settling time using an auxiliary power stage which adjusts its output current to a load current in the transient state. It also achieves a low output ripple voltage using a comparator with a complete comparison signal. The proposed D-LDO was fabricated using a 65-nm CMOS process with an area of 0.0056 μ㎡. The undershoot and overshoot were 47 mV and 23 mV, respectively, when the load current was changed from 10 mA to 100 mA within an edge time of 20 ns. The settling time decreased from 2.1 ㎲ to 130 ns and the ripple voltage was 3 mV with a quiescent current of 75 ㎂.

A Fast RSSI using Novel Logarithmic Gain Amplifiers for Wireless Communication

  • Lee, Sung-Ho;Song, Yong-Hoon;Nam, Sang-Wook
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.9 no.1
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    • pp.22-28
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    • 2009
  • This paper presents a fast received signal strength indicator (RSSI) circuit for wireless communication application. The proposed circuit is developed using power detectors and an analog-to-digital converter to achieve a fast settling time. The power detector is consisted of a novel logarithmic variable gain amplifier (VGA), a peak detector, and a comparator in a closed loop. The VGA achieved a wide logarithmic gain range in a closed loop form for stable operation. For the peak detector, a fast settling time and small ripple are obtained using the orthogonal characteristics of quadrature signals. In $0.18-{\mu}m$ CMOS process, the RSSI value settles down in $20{\mu}s$ with power consumption of 20 mW, and the maximum ripple of the RSSI is 30 mV. The proposed RSSI circuit is fabricated with a personal handy-phone system transceiver. The active area is $0.8{\times}0.2\;mm^2$.

Multi-Phase Buck Converter with Fast Transient Response (빠른 응답을 갖는 멀티페이스 벅 변환기)

  • Lee, Yoon-Jae;Roh, Jeongjin
    • Journal of IKEEE
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    • v.20 no.3
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    • pp.314-317
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    • 2016
  • Recently, efforts to maximize battery life in progress with an increase in the demand for portable devices. In this paper, we propose multi-phase buck converter with fast transient response. Multi-phase buck converter may be used for the output capacitor of small size because the ripple cancellation effect, it is possible to use an inductor having an inductance less. The portable device for quick change from standby mode to active 4-phase design structure was given a fast transient response. The proposed multi-phase buck converter was fabricated using a 0.18 um CMOS process and the supply voltage ranges from 2.7V to 3.3V, the maximum load current is 500mA and settling time is 10us.

A Study on the Stabilization of Gun Barrel by Viscoelastic Damping Material (점탄성 감쇠재료를 이용한 포신 잔류진동의 조기 안정화 방안연구)

  • 임재희;백판구;이재영;정백기
    • Journal of KSNVE
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    • v.9 no.4
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    • pp.714-719
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    • 1999
  • Because the residual vibration of a gun barrel acts negatively on the firing of a large calibers gun, the fast stabilization of theresidual vibration is indispensible to the precise and successive firing. In this study, the residual vibrations of a gun barrel carrying a bore evacuator and a muzzle brake are investigated by the experimental method. The influence of the eigenfrequencies and the mode shapes of gun barrel on the fast stabilization of the residual vibration is studied for the various masses of bore evacuator and muzzle brake, the possition of bore evacutor. Also the relationships between the funcamental frequencies and the settling times of the gun barrel are investigated for the various parameters. The experiments to reduce the residual vibration using the viscoelastic damping treatment gives the best result among the various treatments for the reduction of residual vibration of the system.

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A Low-Voltage High-Performance CMOS Feedforward AGC Circuit for Wideband Wireless Receivers

  • Alegre, Juan Pablo;Calvo, Belen;Celma, Santiago
    • ETRI Journal
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    • v.30 no.5
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    • pp.729-734
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    • 2008
  • Wireless communication systems, such as WLAN or Bluetooth receivers, employ preamble data to estimate the channel characteristics, introducing stringent settling-time constraints. This makes the use of traditional closed-loop feedback automatic gain control (AGC) circuits impractical for these applications. In this paper, a compact feedforward AGC circuit is proposed to obtain a fast-settling response. The AGC has been implemented in a 0.35 ${\mu}m$ standard CMOS technology. Supplied at 1.8 V, it operates with a power consumption of 1.6 mW at frequencies as high as 100 MHz, while its gain ranges from 0 dB to 21 dB in 3 dB steps through a digital word. The settling time of the circuit is below 0.25 ${\mu}s$.

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An Enhanced Finite-Settling-Step Direct Torque and Flux Control (FSS-DTFC) for IPMSM Drives

  • Kim, Sehwan;Seok, Jul-Ki
    • Journal of Power Electronics
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    • v.16 no.4
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    • pp.1367-1374
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    • 2016
  • This paper presents a discrete-time version of voltage and current limited operation using an enhanced direct torque and flux control method for interior permanent magnet synchronous motor (IPMSM) drives. A command voltage vector for airgap torque and stator flux regulation can be uniquely determined by the finite-settling-step direct torque and flux control (FSS-DTFC) algorithm under physical constraints. The proposed command voltage vector trajectories can be developed to achieve the maximum inverter voltage utilization for the discrete-time current limit (DTCL)-based FSS-DTFC. The algorithm can produce adequate results over a number of the potential secondary upsets found in the steady-state current limit (SSCL)-based DTFC. The fast changes in the torque and stator flux linkage improve the dynamic responses significantly over a wide constant-power operating region. The control strategy was evaluated on a 900W IPMSM in both simulations and experiments.