• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2000.10a
• /
• pp.499-503
• /
• 2000

The use of Multiple-Valued FFT(Fast fourier Transform) is extended from binary to multiple-valued logic(MVL) circuits. A multiple-valued FFT circuit can be implemented using current-mode CMOS techniques, reducing the transitor, wires count between devices to half compared to that of a binary implementation. For adder processing in FFT, We give the number representation using such redundant digit sets are called redundant positive-digit number representation and a Redundant set uses the carry-propagation-free addition method. As the designed Multiple-valued FFT internally using PD(positive digit) adder with the digit set 0,1,2,3 has attractive features on speed, regularity of the structure and reduced complexities of active elements and interconnections. for the mutiplier processing, we give Multiple-valued LUT(Look up table)to facilitate simple mathmatical operations on the stored digits. Finally, Multiple-valued 8point FFT operation is used as an example in this paper to illuatrates how a multiple-valued FFT can be beneficial.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.52 no.2
• /
• pp.97-105
• /
• 2015

This paper discusses the implementation of Bruun's FFT on a SIMD processor. FFT is an algorithm used in digital signal processing area and its effective processing is important in the enhancement of signal processing performance. Bruun's FFT algorithm is one of fast Fourier transform algorithms based on recursive factorization. Compared to popular Cooley-Tukey algorithm, it is advantageous in computations because most of its operations are based on real number multiplications instead of complex ones. However it shows more complicated data alignment patterns and requires a larger memory for storing coefficient data in its implementation on a SIMD processor. According to our experiment result, in the processing of the FFT with 1024 complex input data on a SIMD processor, The Bruun's algorithm shows approximately 1.2 times higher throughput but uses approximately 4 times more memory (20 Kbyte) than the Cooley-Tukey algorithm. Therefore, in the case with loose constraints on silicon area, the Bruun's algorithm is proper for the processing of FFT on a SIMD processor.

• The Journal of the Institute of Internet, Broadcasting and Communication
• /
• v.8 no.4
• /
• pp.89-95
• /
• 2008

In the maritime communication, Orthogonal Frequency Division Multiplexing (OFDM) communication terminal should be operated with low power consumption, because the communication should be accomplished in the circumstance of disaster. Therefore, Low power FFT processor is required to be designed with current mode signal processing technique than digital signal processing. Current- to-Voltage Converter (IVC) is a device that converts the output current signal of FFT processor into the voltage signal. In order to lessen the power consumption of OFDM terminal, IVC should be designed with low power design technique and IVC should have wide linear region for avoiding distortion of signal voltage. To design of one-chip of the FFT LSI and IVC, IVC should have a small chip size. In this paper, we proposed the new IVC with wide linear region. We confirmed that the proposed IVC operates linearly within 0.85V to 1.4V as a function of current-mode FFT output range of -100~100[uA]. Designed IVC will contribute to realization of low-power maritime data communication using OFDM system.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.47 no.10
• /
• pp.36-42
• /
• 2010

FFT(Fast Fourier Transform) processor is one of the key components in the implementation of OFDM systems for many wireless standards such as IEEE 802.22. To improve the performances of FFT processors, various studies have been carried out to reduce the complexities of multipliers, memory interface, control schemes and so on. While the number of FFT stages increases logarithmically $log_2N$) as the FFT point-size (N) increases, the number of required registers (or, memories) increases linearly. In large point-size FFT designs, the registers occupy more than 70% of the chip area. In this paper, to reduce the memory size of IFFT for OFDM transmitters, we propose a new IFFT design method based on a combined mapping of modulated data, pilot and null signals. The proposed method focuses on reducing the sizes of the registers in the first two stages of the IFFT architectures since the first two stages require 75% of the total registers. By simulations of 2048-point IFFT design for cognitive radio systems, it is shown that the proposed IFFT design method achieves more than 38.5% area reduction compared with previous IFFT designs.

• ETRI Journal
• /
• v.30 no.3
• /
• pp.451-460
• /
• 2008

Recently, the power consumption of integrated circuits has been attracting increasing attention. Many techniques have been studied to improve the power efficiency of digital signal processing units such as fast Fourier transform (FFT) processors, which are popularly employed in both traditional research fields, such as satellite communications, and thriving consumer electronics, such as wireless communications. This paper presents solutions based on parallel architectures for high throughput and power efficient FFT cores. Different combinations of hybrid low-power techniques are exploited to reduce power consumption, such as multiplierless units which replace the complex multipliers in FFTs, low-power commutators based on an advanced interconnection, and parallel-pipelined architectures. A number of FFT cores are implemented and evaluated for their power/area performance. The results show that up to 38% and 55% power savings can be achieved by the proposed pipelined FFTs and parallel-pipelined FFTs respectively, compared to the conventional pipelined FFT processor architectures.

• Proceedings of the Korea Information Processing Society Conference
• /
• 2008.05a
• /
• pp.1029-1030
• /
• 2008

FFT(Fast Fourier Transform)는 디지털신호처리에 폭넓게 사용되며 특히 여러 OFDM 시스템에 FFT 처리 과정은 꼭 필요한 부분이다. 본 논문에서는 802.11a W-LAN 에 사용되는 64-point FFT 프로세서를 설계하였다. 설계된 FFT 프로세서는 Radix-$2^3$ 알고리즘을 사용하였으며 저면적복소곱셈기를 사용하여 FFT 프로세서의 면적을 줄이는 방법을 제안한다. 기존의 방식에서 네 개의 실수 곱셈기와 두 개의 덧셈기로 구성되는 복소 곱셈기를 두 개의 실수 곱셈기와 한 개의 덧셈기가 수행하도록 설계하였다. 제안한 FFT 프로세서는 VHDL 로 구현되었고 Quartus 4.2 에서 합성되었다. 합성결과 기존 방식에 비해 약 21%의 면적효율이 발생하였다.

• Proceedings of the Korea Information Processing Society Conference
• /
• 2005.05a
• /
• pp.1777-1780
• /
• 2005

OFDM(Orthogonal Frequency Division Multiplexing)은 제 4 세대 기술로 일컬어지는 변조 방식으로 최근 유럽의 디지털 오디오 방송(DAB)과 디지털 비디오 방송(DVB)에 표준으로 사용되고 있으며, IEEE 802.11a 무선 LAN 및 디지털 가입자라인 xDSL 에서도 사용되고 있다. 본 논문에서는 OFDM 모뎀 구현의 핵심이라고 할 수 있는 64-포인트 FFT(Fast Fourier Transform) 프로세서의 여러 가지 구조를 분석하고, 이들과 비교하여 성능 대 면적 비를 획기적으로 향상시킨 새로운 FFT 프로세서인 Radix-4,2 SIC (Single Instruction Computer) 구조를 제안하였다. 본 논문에서 제안하는 SIC 구조는 버터플라이 연산의 재사용을 극대화하였으며 Radix-4,2 알고리즘을 사용함으로써 FFT 프로세서에서 면적의 80%를 차지하는 복소곱셈기의 수를 감소시켜 크기를 획기적으로 줄인 결과를 보여 준다.

• ETRI Journal
• /
• v.29 no.1
• /
• pp.79-88
• /
• 2007

This paper proposes a novel concept of adjusting the hardware size in a multi-carrier code division multiple access (MC-CDMA) receiver in real time as per the channel parameters such as delay spread, signal-to-noise ratio, transmission rate, and Doppler frequency. The fast Fourier transform (FFT) or inverse FFT (IFFT) size in orthogonal frequency division multiplexing (OFDM)/MC-CDMA transceivers varies from 1024 points to 16 points. Two low-power reconfigurable radix-4 256-point FFT processor architectures are proposed that can also be dynamically configured as 64-point and 16-point as per the channel parameters to prove the concept. By tailoring the clock of the higher FFT stages for longer FFTs and switching to shorter FFTs from longer FFTs, significant power saving is achieved. In addition, two 256 sub-carrier MC-CDMA receiver architectures are proposed which can also be configured for 64 sub-carriers in real time to prove the feasibility of the concept over the whole receiver.

• Journal of Biomedical Engineering Research
• /
• v.6 no.2
• /
• pp.15-22
• /
• 1985

We have developed a microprogramir!able signal processor for real-time ultrasonic signal processing. Processing speed was increased by the parallelism in horizontal microprogram using 104bits microcode and the Pipelined architecture. Control unit of the signal processor was designed by microprogrammed architec- ture and writable control store (WCS) which was interfaced with host computer, APPLE- ll . This enables the processor to develop and simulate various digital signal processing algorithms. The performance of the processor was evaluated by the Fast Fourier Transform (FFT) program. The execution time to perform 16 bit 1024 points complex FF7, radix-2 DIT algorithm, was about 175 msec with IMHz master Clock. We can use this processor to Bevelop more efficient signal processing algorithms on the biological signal processing.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.27 no.2
• /
• pp.144-150
• /
• 1990

This paper describes radix-4 Fast Fourier Transform (FFT) Processor designed with the new twice perfect shuffle developed from a perfect shuffle used in radix-2 FFT algorithm. The FFT Processor consists of a butterfly arithmetic circuit, address generators for input, output and coefficient, input and output registers and controller. Also, it requires the external ROM for storage of coefficient and RAM for input and output. The butterfly circuit includes 12 bit-serial ($16{\times}8$) multipliers, adders, subtractors and delay shift registers. Operating on 25 MHz two phase clock, this processor can compute 256 point FFT in 6168 clocks, i.e. 247 us and provides flexibility by allowing the user to select any size among 4,16,64,and256points. Being fabricated with 2-um double metal CMOS process, it includes about 28000 transistors and 55 pads in $8.0{\times}8.2mm^2$area.