• Title/Summary/Keyword: Fabricated design area

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Design and Fabrication of Monopole Antenna with Three Branch Strips and Rectangular Slit Ground for WLAN/WiMAX Applications (무선랜과 와이맥스 시스템에 적용 가능한 브랜치 라인과 사각 슬릿 접지를 갖는 모노폴 안테나 설계와 제작)

  • Koo, Yung-Seo;Yoon, Joong-Han
    • The Journal of the Korea institute of electronic communication sciences
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    • v.6 no.5
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    • pp.611-620
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    • 2011
  • A planar monopole antenna that was developed for WLAN/WiMAX application is presented in this paper. The proposed antenna with three strips, an asymmetrical ground plane, and a rectangular slit in the ground is designed to cover the popular frequency spectrum of WLAN (wireless local area network) bands and WiMAX (Worldwide Interoperability for Microwave Access) bands. The proposed antenna, which is capable of wideband operation, is fed by a strip line and fabricated on an FR-4 substrate. The obtained numerical results agree well with the experiment data. It was validated that the configuration can meet the demands for the WLAN/WiMAX systems and effectively enhanced the impedance bandwidth to 9.95% for the lower band and 76.05% for the upper band for VSWR < 1 : 2. This paper also presents and discusses the 2D radiation patterns and 3D gains according to the results of the experiment.

Design of a Built-In Current Sensor for CMOS IC Testing (CMOS 집적회로 테스팅을 위한 내장형 전류 감지 회로 설계)

  • Kim, Tae-Sang;Hong, Seung-Ho;Kwak, Chul-Ho;Kim, Jeong-Beam
    • Journal of IKEEE
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    • v.9 no.1 s.16
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    • pp.57-64
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    • 2005
  • This paper presents a built-in current sensor(BICS) that detects defects in CMOS integrated circuits using the current testing technique. This circuit employs a cross-coupled connected PMOS transistors, it is used as a current comparator. The proposed circuit has a negligible impact on the performance of the circuit under test (CUT) and high speed detection time. In addition, in the operation of the normal mode, the BlCS does not have dissipation of extra power, and it can be applied to the deep submicron process. The validity and effectiveness are verified through the HSPICE simulation on circuits with defects. The area overhead of a BlCS versus the entire chip is about 9.2%. The chip was fabricated with Hynix $0.35{\mu}m$ 2-poly 4-metal N-well CMOS standard technology.

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Planar Slot Wideband Antenna for Multiple Communication Services (다중 통신서비스를 위한 평판 슬롯 광대역 안테나)

  • Park, Dong-Kook;Bataller, Miguel Ferrando
    • Journal of IKEEE
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    • v.24 no.1
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    • pp.90-96
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    • 2020
  • As various communication services have emerged due to the development of mobile communication technology, there is a need for a wideband antenna supporting multiple communication services with one antenna. In this paper, we propose a planar slot wideband antenna that can support all the communication services of 3.1~4.99GHz, the low frequency band of 5G, in addition to the existing communication services such as WiFi, LTE 2300/2500, and WiMAX. Through the simulation, the optimized antenna design parameters were obtained, and the antenna was fabricated to implement an antenna with a frequency bandwidth of 1.96~6.01GHz (S11 <-10dB) and presented the radiation pattern and gain of the antenna. The proposed antenna is a multi-band antenna that can provide all the services of LTE, Wifi, WiMAX, and 5G low frequency bands. It can be used as a repeater antenna in radio shadow area such as buildings, dense areas, and ships.

A study on the impact load acting on an FPSO bow by steep waves

  • Hong, Sam-Kwon;Lew, Jae-Moon;Jung, Dong-Woo;Kim, Hee-Taek;Lee, Dong-Yeon;Seo, Jong-Soo
    • International Journal of Naval Architecture and Ocean Engineering
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    • v.9 no.1
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    • pp.1-10
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    • 2017
  • Various offshore structures such as FPSO, FSO, Semi-submersible, TLP and Spar are operated to develop offshore oil and gas fields. Most of the offshore structures shall be operated over 20 years under the harsh environments at sites so that the offshore structures should be designed to endure the harsh environments. In this study, the effect of the impact load (so called slapping load) by the steep waves acting on the FPSO bow is investigated through the model test. For measurement of the impact pressures on the frontal area, a bow-shaped panel was fabricated, and installed the pressure sensors on the bow starboard side of the model FPSO. During the model test campaign, the impact load was investigated using the steep waves with $Hs/{\lambda}$ greater than 1/16 of the representative wave condition. Consequently, it is confirmed through the model test that the impact loads acting on the FPSO bow are significantly increased with the steep waves ($Hs/{\lambda}$ > 1/16) than the representative wave conditions of a maximum significant wave height and a pitch forcing period. Therefore, for safe design of North Sea FPSO, it is necessary to consider the steep waves in addition to the representative wave conditions and to be applied as proper structural load. Also, the effect of random seeds in irregular waves should be considered to build the safe FPSO.

Design of a 10 bit Low-power current-mode CMOS A/D converter with Current predictors (전류예측기를 이용한 10비트 저전력 전류구동 CMOS A/D 변환기 설계)

  • 심성훈;권용복;윤광섭
    • Journal of the Korean Institute of Telematics and Electronics C
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    • v.35C no.10
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    • pp.22-29
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    • 1998
  • In this paper, an 10 bit current-mode CMOS A/D converter with a current predictor is designed with a CMOS process to be integrated into a portable image signal processing system. A current predictor let the number of comparator reduce to 70 percent compared with the two step flash architecture. The current magnitude of current reference is reduced to 68 percent with a modular current reference. The designed 10 bit Low-power current-mode CMOS A/D converter with a current predictor is simulated with HSPICE using 0.6$\mu\textrm{m}$ N-well single-poly triple-metal CMOS process parameters. It results in a conversion rate of 10MSamples/s. A power consumption is measured to be 94.4mW at single +5V supply voltage. The 10 bit A/D converter fabricated using the same process occupies the chip area of 1.8mm x 2.4mm.

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Class-D Digital Audio Amplifier Using 1-bit 4th-order Delta-Sigma Modulation (1-비트 4차 델타-시그마 변조기법을 이용한 D급 디지털 오디오 증폭기)

  • Kang, Kyoung-Sik;Choi, Young-Kil;Roh, Hyung-Dong;Nam, Hyun-Seok;Roh, Jeong-Gin
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.45 no.3
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    • pp.44-53
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    • 2008
  • In this paper, we present the design of delta-sigma modulation-based class-D amplifier for driving headphones in portable audio applications. The presented class-D amplifier generates PWM(pulse width modulation) signals using a single-bit fourth-order high-performance delta-sigma modulator. To achieve a high SNR(signal-to-noise ratio) and ensure system stability, the locations of the modulator loop filter poles and zeros are optimized and thoroughly simulated. The test chip is fabricated using a standard $0.18{\mu}m$ CMOS process. The active area of the chip is $1.6mm^2$. It operates for the signal bandwidth from 20Hz to 20kHz. The measured THD+N(total harmonic distortion plus noise) at the $32{\Omega}$ load terminal is less than 0.03% from a 3V power supply.

Design of a CMOS IF PLL Frequency Synthesizer (CMOS IF PLL 주파수합성기 설계)

  • 김유환;권덕기;문요섭;박종태;유종근
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.40 no.8
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    • pp.598-609
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    • 2003
  • This paper describes a CMOS IF PLL frequency synthesizer. The designed frequency synthesizer can be programmed to operate at various intermediate frequencies using different external LC-tanks. The VCO with automatic amplitude control provides constant output power independent of the Q-factor of the external LC-tank. The designed frequency divider includes an 8/9 or 16/17 dual-modulus prescaler and can be programmed to operate at different frequencies by external serial data for various applications. The designed circuit is fabricated using a 0.35${\mu}{\textrm}{m}$ n-well CMOS process. Measurement results show that the phase noise is 114dBc/Hz@100kHz and the lock time is less than 300$mutextrm{s}$. It consumes 16mW from 3V supply. The die area is 730${\mu}{\textrm}{m}$$\times$950${\mu}{\textrm}{m}$.

Compact Dual-band CPW-fed Slot Antenna Using Split-Ring Resonator (분할 링 공진기를 이용한 소형 이중 대역 CPW-급전 슬롯 안테나)

  • Yeo, Junho;Park, Jin-Taek;Lee, Jong-Ig
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.19 no.11
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    • pp.2526-2533
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    • 2015
  • In this paper, a design method for a compact dual-band coplanar waveguide-fed slot antenna using SRR(split-ring resonator) conductor is studied. The SRR conductor is loaded inside a rectangular slot of the proposed antenna for dual-band operation. When the SRR conductor is inserted into the slot, the original rectangular slot is divided into a rectangular loop region and a rectangular slot region, and frequency bands are created by the loop and slot, separately. A prototype of the proposed dual-band slot antenna operating at 2.45 GHz WLAN band and 3.40-5.35 GHz band is fabricated on an FR4 substrate with a dimension of 30 mm by 30 mm. Experiment results show that the antenna has a desired impedance characteristic with a frequency band of 2.38-2.51 GHz and 3.32-5.38 GHz for a voltage standing wave < 2, and measured gain is 1.7 dBi at 2.45 GHz, and it ranges 2.4-3.2 dBi in the second band.

A NARX Dynamic Neural Network Platform for Small-Sat PDM (동적신경망 NARX 기반의 SAR 전력모듈 안전성 연구)

  • Lee, Hae-Jun
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.24 no.6
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    • pp.809-817
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    • 2020
  • In the design and development process of Small-Sat power distribution and transmission module, the stability of dynamic resources was evaluated by a deep learning algorithm. The requirements for the stability evaluation consisted of the power distribution function of the power distribution module and demand module to the SAR radar in Small-Sat. To verify the performance of the switching power components constituting the power module PDM, the reliability was verified using a dynamic neural network. The adoption material of deep learning for reliability verification is the power distribution function of the payload to the power supplied from the small satellite main body. Modeling targets for verifying the performance of this function are output voltage (slew rate control), voltage error, and load power characteristics. First, to this end, the Coefficient Structure area was defined by modeling, and PCB modules were fabricated to compare stability and reliability. Second, Levenberg-Marquare based Two-Way NARX neural network Sigmoid Transfer was used as a deep learning algorithm.

Towards reducing acoustical high-frequency noise of a direct current relay via contact structure (직류 계전기의 접촉구조에 의한 고주파수 소음저감)

  • Junhyeok, Yang;Jongseob, Won;Wonjin, Kim
    • The Journal of the Acoustical Society of Korea
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    • v.41 no.6
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    • pp.691-697
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    • 2022
  • In this work, a straightforward component design of a direct current (DC) relay equipped in electric vehicles is discussed. The work aims to provide and evaluate effective measures for reducing high-frequency sound from the DC relay carrying electric power. From the operation experiments for the relay, it is observed that noise is caused by the resonance from the forced vibration by the electromagnetic repulsive force originating at the area of electric contacts with a resonance frequency of around 710 Hz ~ 730 Hz. A finite element model for the relay was established to conduct vibration mode analysis, consisting of stationary and movable contacts and a contact spring. Vibration mode analysis indicates that in the resonance frequency, the movable contact with two-point contacts experiences rotational vibration mode. For the proposed relay with a three-point contact, vibration mode analyses give reasonable results of reducing noise at that frequency. Furthermore, for the fabricated relays with the three-point contact, similar results have been obtained. In conclusion, one can see that the proposed measures provide one of the feasible solutions to the reduction of relay noise.