• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.9A
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• pp.1401-1410
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• 1999

In this paper, we propose a fast block matching algorithm using the lower and upper bound of mean absolute difference (MAD) which is calculated at the search region overlapped with neighbor blocks. At first, we calculate the lower bound of MAD and reduce the search point by using this lower bound. In this method, we can get good prediction error performance close to full search block matching algorithm (FSBMA), but there exists some computational complexity that has to be reduced. Therefore, we further reduce the computational complexity by using pixel subsampling besides the lower and upper bound of MAD. Experimental results show that we can remarkably reduce the computational complexity with good prediction error performance close to FSBMA.

• ETRI Journal
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• v.37 no.4
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• pp.772-779
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• 2015

This paper presents a power-efficient hardware realization for a motion estimation technique that is based on the full-search block matching algorithm (FSBMA). The considered input is the quarter common intermediate format of digital video. The mean of absolute difference (MAD) is the distortion criteria employed for the block matching process. The conventional architecture considered for the hardware realization of FSBMA is that of the shift register-based 2-D systolic array. For this architecture, a conservative approximation technique is adapted to eliminate unnecessary MAD computations involved in the block matching process. Upon introducing the technique to the conventional architecture, the power and complexity of its implantation is reduced, while the accuracy of the motion vector extracted from the block matching process is preserved. The proposed architecture is verified for its functional specifications. A performance evaluation of the proposed architecture is carried out using parameters such as power, area, operating frequency, and efficiency.

• Proceedings of the Korea Information Processing Society Conference
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• 2006.05a
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• pp.153-156
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• 2006

본 논문에서는 H.264 표준화 기구인 Joint Video Team(JVT) 권고안의 정수 단위 화소 움직임 예측을 위한 Unsymmetrical-cross Multi-Hexagon-grid Search(UMHexagonS) 알고리즘에서 Uneven Multi-Hexagon-grid Search(UMHGS) 부분을 개선한 알고리즘을 제안한다. 제안하는 알고리즘은 이전 프레임의 동일위치 또는 상위 모드에서 이미 선택된 움직임 벡터(MV: Motion Vector)를 이용하여 신호 대 잡음 비(PSNR: Peak Signal to Noise Ratio) 및 평균 비트 율(Average Bitrates)을 유지하면서, 현재 매크로블록의 검색영역을 줄이는 것이 가능하다. 제안하는 알고리즘의 성능은 Full Search Block Matching Algorithm(FSBMA) 및 UMHexagonS 알고리즘의 integer pel 에 대한 SAD(Sum of Absolute Difference) 연산횟수로 비교평가 하였다. 그 결과, FSBMA 에 비하여 평균 97.64%, UMHexagonS 에 비하여는 평균 17.48%의 연산횟수를 감소시키는 우수함을 보였다.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.887-890
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• 1998

We present a novel multi-resolution block matching algorithm (BMA) for fast motion estimation. At the coarsest level, a full search BMA (FSBMA) is performed for searching complex or random motion. Concurrently, spatial correlation of motion vector (MV) field is used for searching continuous motion. Here we present an efficient method for searching full resolution MVs without MV decimation even at the coarsest leve. After the coarsest level search, two or three initial MV candidates are chosen for the next level. At the further levels, the MV candidates are refined within much smaller search areas. Simulation results show that in comparison with FSBMA, the proposed BMA achieves a speed-up factor over 710 with minor PSNR degradation of 0.2dB at most, under a normal MPEG2 coding environment. Furthermore, our scheme is also suitable for hardware implementation due to regular data-flow.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.36S no.11
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• pp.102-111
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• 1999

In this paper, we propose a fast full search block matching algorithm using the search region subsampling and the difference of adjacent pixels in current block. In the proposed algorithm, we calculate the lower bound of mean absolute difference (MAD) at each search point using the MAD value of neighbor search point and the difference of adjacent pixels in current block. After that, we perform block matching process only at the search points that need block matching process using the lower bound of MAD at each search point. To calculate the lower bound of MAD at each search point, we need the MAD value of neighbor search point. Therefore, the search points are subsampled at the factor of 4 and the MAD value at the subsampled search points are calculated by the block matching process. And then, the lower bound of MAD at the rest search points are calculated using the MAD value of the neighbor subsampled search point and the difference of adjacent pixels in current block. Finally, we discard the search points that have the lower bound of MAD value exceed the reference MAD which is the minimum MAD value of the MAD values at the subsampled search points and we perform the block matching process only at the search points that need block matching process. By doing so, we can reduce the computation complexity drastically while the motion compensated error performance is kept the same as that of full search block matching algorithm (FSBMA). The experimental results show that the proposed method has a much lower computational complexity than that of FSBMA while the motion compensated error performance of the proposed method is kept same as that of FSBMA.

• Journal of Animal Science and Technology
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• v.57 no.3
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• pp.11.1-11.8
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• 2015

An experiment was conducted to evaluate apparent (AID) and standardized (SID) ileal digestibilities of crude protein (CP) and amino acids (AA) with 6 soybean products in weaning pigs. A total of 14 weaning barrows with an initial body weight of $6.54{\pm}0.34kg$ were fitted with T-cannula at the distal ileum and allotted to 7 diets containing various soybean products. The soybean products used in the experiment were conventional soybean meal (CSBM), SBM fermented by Aspergillus oryzae GB-107 (FSBMA), SBM fermented by Bacillus subtilis PP6 (FSBMB), UV sterilized SBM fermented by Bacillus subtilis PP6 (UVFSBMB), SBM containing Bacillus subtilis PP6 (PSBM), and soy protein concentrate (SPC). Six corn-based diets were used and each of soybean products was added. All diets contained 5.0 g/kg of chromic oxide as an indigestible indicator and an N-free diet was used to measure basal endogenous losses of CP and AAs. Ileal CP digestibility did not differ by different soybean products. However, SIDs of Ile, Phe and Val were improved in pigs fed the FSBMB, UVFSBMB and SPC diets and the pigs fed the FSBMA diet showed higher SIDs of Phe and Val compared with those fed the CSBM diet (P < 0.05). The FSBMB diet had higher SIDs in most AAs compared with the FSBMA diet (P < 0.05), and higher SIDs of Lys, Ala, Pro, Ser, and Tyr compared with PSBM diet (P < 0.05). However, there was no response of UV-sterilization on the FSBMB in the SIDs of AAs. These results suggest that SIDs of AAs could be improved by the supplementation of fermented soybean products in the diet for weaning pigs but fermentation with Bacillus subtilis is more efficient in improving ileal AA digestibility than that with Aspergillus oryzae. Furthermore, probiotics supplementation in the CSBM and UV-sterilization of the FSBMB had no effects on chemical composition and ileal AA digestibility.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.5A
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• pp.503-509
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• 2007

Low-power motion estimation is required for video coding in portable information devices. In this paper, we propose a low-power motion estimation algorithm and 1-D systolic may VLSI architecture using full search block matching algorithm (FSBMA). Main power dissipation sources of FSBMA are complex computations and frequent memory accesses for data in the search area. In the proposed algorithm, memory accesses and computations are reduced by using 1D PE (processing array) array architecture performing motion estimation of two neighboring blocks in parallel and by skipping unnecessary computations during motion estimation. The VLSI implementation results of the algorithm show that the proposed VLSI architecture can save 9.3% power dissipation and can operate two times faster than an existing low-power motion estimator.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.601-604
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• 1999

We propose a new hierarchical motion estimator architecture that supports the advanced prediction mode of recent low bit-rate video coders such as H.263 and MPEG-4. In the proposed VLSI architecture, a basic searching unit (BSU) is commonly utilized for all hierarchical levels to make a systematic and small sized motion estimator. Since the memory bank of the proposed architecture provides scheduled data flow for calculating 8$\times$8 block-based sum of absolute difference (SAD), both a macroblock-based motion vector (MV) and four block-based MVs are simultaneously obtained for each macroblock in the advanced prediction mode. The proposed motion estimator gives similar coding performance compared with full search block matching algorithm (FSBMA) while achieving small size and satisfying the advanced prediction mode.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2006.11a
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• pp.121-124
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• 2006

본 논문에서는 영상 압축에 있어서 사용되는 새로운 고속 움직임 추정 기법에 대해 소개한다. 전역 탐색 블록 정합 알고리즘(FSBMA)은 최상의 PSNR을 갖는 화질로 움직임 벡터를 추정할 수 있지만 높은 계산량으로 인하여 실시간 구현에 부적합하다는 단점을 가지고 있다. 그러므로 계산량을 낮추면서 유사한 화질을 유지할 수 있는 많은 고속 탐색 기법들이 제안되어 왔다. 본 논문에서는 기존의 잘 알려진 고속 블록 정합 알고리즘을 수정 보완한 새로운 알고리즘을 제안한다. 제안한 방법에서는 움직임 추정에서의 고속 블록 정합 알고리즘에 있어 변형된 다이아몬드(Diamond) 탐색 기법을 이용하여 영상이 갖는 서로 다른 움직임 패턴에 대해 움직임의 방향성에 따라 적응적으로 탐색 방향과 패턴을 달리하면서 움직임을 예측하여 다이아몬드(Diamond)탐색 알고리즘과 유사한 화질을 유지하면서 보다 적은 계산량을 가지고 움직임 벡터를 추정학 수 있다. 또한 이를 PMVFAST(Predictive Motion Vector Field Adaptive Search Technique)와 결합함으로서 보다 좋은 화질을 가질 수 있다.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.43 no.4 s.310
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• pp.55-65
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• 2006

Most of fast block motion estimation algorithms reported so far in literatures aim to reduce the computation in terms of the number of search points, thus do not fit well with multimedia processors due to their irregular data flow. For multimedia processors, proper reuse of data is more important than reducing number of absolute difference operations because the execution cycle performance strongly depends on the number of off-chip memory access. Therefore, in this paper, we propose a Hexagon-shape line search (HEXSLS) algorithm using line search pattern which can increase data reuse from on-chip local buffer, and check sub-sampling points in line search pattern to reduce unnecessary SAD operation. Our experimental results show that the prediction error (MAE) performance of the proposed HEXSLS is similar to that of the full search block matching algorithm (FSBMA), while compared with the hexagon-based search (HEXBS), the HEXSLS outperforms. Also the proposed HEXSLS requires much lesser off-chip memory access than the conventional fast motion estimation algorithm such as the hexagon-based search (HEXBS) and the predictive line search (PLS). As a result, the proposed HEXSLS algorithm requires smaller number of execution cycles on media processor.