Proceedings of the IEEK Conference (대한전자공학회:학술대회논문집)
- 1999.06a
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- Pages.601-604
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- 1999
A New VLSI Architecture of a Hierarchical Motion Estimator for Low Bit-rate Video Coding
저전송률 동영상 압축을 위한 새로운 계층적 움직임 추정기의 VLSI 구조
Abstract
We propose a new hierarchical motion estimator architecture that supports the advanced prediction mode of recent low bit-rate video coders such as H.263 and MPEG-4. In the proposed VLSI architecture, a basic searching unit (BSU) is commonly utilized for all hierarchical levels to make a systematic and small sized motion estimator. Since the memory bank of the proposed architecture provides scheduled data flow for calculating 8
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