• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2016.10a
• /
• pp.158-160
• /
• 2016

전자서명(ECDSA), 키 교환(ECDH) 등에 사용되는 233-비트 타원곡선 암호(Elliptic Curve Cryptography; ECC) 프로세서의 설계에 대해 기술한다. $GF(2^{333})$ 상의 덧셈, 곱셈, 나눗셈 등의 유한체 연산을 지원하며, 하드웨어 자원 소모가 적은 쉬프트 연산과 XOR 연산만을 이용하여 구현하였다. 스칼라 곱셈은 modified montgomery ladder 알고리듬을 이용하여 구현하였으며, 정수 k의 정보를 노출하지 않고, 단순 전력분석에 보다 안전하다. 스칼라 곱셈 연산은 최대 490,699 클록 사이클이 소요된다. 설계된 ECC 프로세서는 Xilinx ISim을 이용한 시뮬레이션 결과값과 한국인터넷진흥원(KISA)의 참조 구현 값을 비교하여 정상 동작함을 확인하였다. Xilinx Virtex5 XC5VSX95T FPGA 디바이스 합성결과 1,576 슬라이스로 구현되었으며, 189 MHz의 최대 동작주파수를 갖는다.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.21 no.6
• /
• pp.1061-1068
• /
• 2017

A RVDT is a sensor that measures angular displacement and the output signal of RVDT is a DSBSC-AM signal. For this reason, a DSBSC-AM demodulation processor is required to determine the angular displacement from the output signal. In this paper, DADC(Digital Angle to DC) which extracts the angular displacement from the output signal of a RVDT is implemented based-on modified Costas Loop usually used in the demodulation of DSBSC-AM signal by using FPGA. DADC can used with both 4-wire and 5-wire RVDTs and can exactly compensate the phase difference between the input excitation and output signals of a RVDT unlike the conventional analog RVDT signal conditioners which require external components. Since digital signal processing technique that can enhance the linearity is exploited, DADC shows 0.035% linearity error, which is smaller than 0.005% that of a conventional analog signal conditioner. The DADC are tested in an integrated experimental environment which includes a commercial RVDT sensor, ADC and an analog output block.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.17 no.3
• /
• pp.699-707
• /
• 2016

This paper proposes a low-complexity central processing unit (CPU) that is suitable for deeply embedded systems, including Internet of things (IoT) applications. The core features a 16-bit instruction set architecture (ISA) that leads to high code density, as well as a multicycle architecture with a counter-based control unit and adder sharing that lead to a small hardware area. A co-processor, instruction cache, AMBA bus, internal SRAM, external memory, on-chip debugger (OCD), and peripheral I/Os are placed around the core to make a system-on-a-chip (SoC) platform. This platform is based on a modified Harvard architecture to facilitate memory access by reducing the number of access clock cycles. The SoC platform and CPU were simulated and verified at the C and the assembly levels, and FPGA prototyping with integrated logic analysis was carried out. The CPU was synthesized at the ASIC front-end gate netlist level using a $0.18{\mu}m$ digital CMOS technology with 1.8V supply, resulting in a gate count of merely 7700 at a 50MHz clock speed. The SoC platform was embedded in an FPGA on a miniature board and applied to deeply embedded IoT applications.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.29 no.11A
• /
• pp.1263-1270
• /
• 2004

A low-power 64-point FFT/IFFT processor core is designed, which is an essential block in OFDM-based wireless LAM modems. The radix-2/418 DIF (Decimation-ln-Frequency) FFT algorithm is implemented using R2SDF (Radix-2 Single-path Delay Feedback) structure. Some design techniques for low-power implementation are considered from algorithm level to circuit level. Based on the analysis on infernal data flow, some unnecessary switching activities have been eliminated to minimize power dissipation. In circuit level, constant multipliers and complex-number multiplier in data-path are designed using truncation structure to reduce gate counts and power dissipation. The 64-point FFT/IFFT core designed in Verilog-HDL has about 28,100 gates, and timing simulation results using gate-level netlist with extracted SDF data show that it can safely operate up to 50-MHz＠2.5-V, resulting that a 64-point FFT/IFFT can be computed every 1.3-${\mu}\textrm{s}$. The functionality of the core was fully verified by FPGA implementation using various test vectors. The average SQNR of over 50-dB is achieved, and the average power consumption is about 69.3-mW with 50-MHz＠2.5-V.

• Journal of IKEEE
• /
• v.24 no.3
• /
• pp.901-908
• /
• 2020

This paper describes a method for scalable hardware implementation of modular inversion. The proposed scalable architecture has a one-dimensional array of processing elements (PEs) that perform arithmetic operations in 32-bit word, and its performance and hardware size can be adjusted depending on the number of PEs used. The hardware operation of the scalable processor for modular inversion was verified by implementing it on Spartan-6 FPGA device. As a result of logic synthesis with a 180-nm CMOS standard cells, the operating frequency was estimated to be in the range of 167 to 131 MHz and the gate counts were in the range of 60,000 to 91,000 gate equivalents when the number of PEs was in the range of 1 to 10. When calculating 256-bit modular inverse, the average performance was 18.7 to 118.2 Mbps, depending on the number of PEs in the range of 1 to 10. Since our scalable architecture for computing modular inversion in GF(p) has the trade-off relationship between performance and hardware complexity depending on the number of PEs used, it can be used to efficiently implement modular inversion processor optimized for performance and hardware complexity required by applications.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.8 no.2
• /
• pp.430-439
• /
• 2004

This paper describes a design of 8192/2048-point FFT/IFFT processor (CFFT8k2k), which performs multi-carrier modulation/demodulation in OFDM-based DVB-T receiver. Since a large size FFT requires a large buffer memory, two design techniques are considered to achieve memory-efficient implementation of 8192-point FFT/IFFT. A hybrid structure, which is composed of radix-4 single-path delay feedback (R4SDF) and radix-4 single-path delay commutator (R4SDC), reduces its memory by 20% compared to R4SDC structure. In addition, a memory reduction of about 24% is achieved by a novel two-step convergent block floating-point scaling. As a result, it requires only 57% of memory used in conventional design, reducing chip area and power consumption. The CFFT8k2k core is designed in Verilog-HDL, and has about 102,000 Bates, RAM of 292k bits, and ROM of 39k bits. Using gate-level netlist with SDF which is synthesized using a $0.25-{\um}m$ CMOS library, timing simulation show that it can safely operate with 50-MHz clock at 2.5-V supply, resulting that a 8192-point FFT/IFFT can be computed every 164-${\mu}\textrm{s}$. The functionality of the core is fully verified by FPGA implementation, and the average SQNR of 60-㏈ is achieved.

• Journal of Advanced Navigation Technology
• /
• v.25 no.4
• /
• pp.305-312
• /
• 2021

Even though various types of sensors are being used for security applications, radar sensors are being suggested as an alternative due to the privacy issues. Among those radar sensors, PD radar has high-complexity receiver, but, FMCW radar requires fewer resources. However, FMCW has disadvantage from the use of 2D-FFT which increases the complexity, and it is difficult to distinguish people from objects those are stationary. In this paper, we present the design and the implementation results of the radar signal processor (RSP) that can distinguish between people and object by respiration measurement using phase estimation without 2D-FFT. The proposed RSP is designed with Verilog-HDL and is implemented on FPGA device. It was confirmed that the proposed RSP includes 6,425 LUT, 4,243 register, and 12,288 memory bits with 92.1% accuracy for target's breathing status.

• Journal of Electrical Engineering and Technology
• /
• v.10 no.4
• /
• pp.1540-1551
• /
• 2015

The detection of position and speed in BLDC motors without using position sensors has meant many efforts for the last decades. The aim of this paper is to develop a sensorless technique for detecting the position and speed of BLDC motors, and to overcome the drawbacks of position sensor-based methods by improving the performance of traditional approaches oriented to motor phase voltage sensing. The position and speed information is obtained by computing the derivative of the terminal phase voltages regarding to a virtual neutral point. For starting-up the motor and implementing the algorithms of the detection technique, a FPGA board with a real-time processor is used. Also, a versatile hardware has been developed for driving BLDC motors through pulse width modulation (PWM) signals. Delta and wye winding motors have been considered for evaluating the performance of the designed hardware and software, and tests with and without load are performed. Experimental results for validating the detection technique were attained in the range 5-1500 rpm and 5-150 rpm under no-load and full-load conditions, respectively. Specifically, speed and position square errors lower than 3 rpm and between 10º-30º were obtained without load. In addition, the speed and position errors after full-load tests were around 1 rpm and between 10º-15º, respectively. These results provide the evidence that the developed technique allows to detect the position and speed of BLDC motors with low accuracy errors at starting-up and over a wide speed range, and reduce the influence of noise in position sensing, which suggest that it can be satisfactorily used as a reliable alternative to position sensors in precision applications.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.43 no.10 s.352
• /
• pp.68-73
• /
• 2006

This, paper proposes a cosimulation methodology that results in an efficient SoC design as well as fast verification by integrating HDL, SystemC, and algorithm-level abstraction using the design tools Active-HDL and Matlab's Simulink. To demonstrate the proposed design methodology, we implemented the design technique on a serial connection multi-channel speaker system. We have demonstrated the proposed cosimulation method utilizing an ARM processor based SoC Master board with the AMBA bus interface and a Xilinx Vertex4 FPGA. The proposed method has the advantage of simultaneous simulation verification of both software and hardware parts in high levels of abstraction mixed with some performance critical parts in more concrete RTL codes. This allows relatively fast and easy design of a speaker connection system which typically requires significant amount of data processing for verification.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.52 no.1
• /
• pp.175-181
• /
• 2015

In this paper, we develop a 2.4GHz ISM band wireless communication platform prototype based on embedded linux which support can be u-Hospital service. The developed system is available connecting between ARM920T processor board and FPGA board and linking IEEE 802.11b PHY board, AD/DA(10Bit) and RF(2.4GHz) board for wireless access. It is also can be utilized for the embedded system design with IEEE 802.11b/g Access Point(Option: IEEE 802.11a/b/g) test due to the Embedded Linux. Also, the developed system is possible to test and verify the radio access technology, Modem(OFDM etc) and IP(Intellectual Property) circuit. And make the most use of the system, we search for a expansion to that home and mobile healthcare, wellness service application.