• Journal of Satellite, Information and Communications
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• v.4 no.1
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• pp.36-44
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• 2009

The key technologies of GNSS receiver for GNSS sensor station are under development as a part of a GNSS ground station in ETRI. This paper presents the GNSS receiver implementation and signal processing result which is implemented based on FPGA to process the Galileo E1 and E5 signal. To verify the working and performance for GNSS receiver which is implemented based on FPGA, live signal received from GIOVE-B which is second test satellite is used. We gather GIOVE-B signal by using prototyping antenna and RF/IF units including IF-component. To verify Galileo E1 and E5 signal processing function from GIOVE-B, FPGA based signal processing module is implemented as a prototyping hardware board.

• Journal of the Korea Society of Computer and Information
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• v.25 no.7
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• pp.1-8
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• 2020

In this paper, we present an implementation of high speed image data transfer using XDMA for a video signal generation / acquisition device developed as a military test equipment. The technology proposed in this study obtains efficiency by replacing the method of copying data using the system buffer in the kernel area with the transmission and reception through the DMA engine in the FPGA. For this study, the device was developed as a PXIe platform in consideration of life cycle, and performance was maximized by using a low-cost FPGA considering mass productivity. The video I/O board implemented in this paper was tested by changing the AXI interface clock frequency and link speed through the existing memory copy method. In addition, the board was constructed using the DMA engine of the FPGA, and as a result, it was confirmed that the transfer speed was increased from 5~8Hz to 140Hz. The proposed method will contribute to strengthening defense capability by reducing the cost of device development using the PXIe platform and increasing the technology level.

• Journal of the Institute of Convergence Signal Processing
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• v.5 no.4
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• pp.333-337
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• 2004

This paper describe a design of 5GHz OFDM baseband chip for IEEE 802.11a wireless LAN. The proposed device is consists of transmitter and receiver within a single FPGA chip. We applied single tap equalizer that use Normalized LMS algorithm to remove ISI that happen at high speed data transmission. And also, we used carrier wave frequency offset algorithm that use training symbol to remove ICI. The simulation results show the correct transmission without errors the between transmitter and receiver And we can remarkably reduce the number of register through the synthesized circuits by using DSP block and EMB(Embedded Memory Block). The target device for implementation of the synthesized circuits is Altera Stratix EPIS25FC672 FPGA and design platform is VHDL.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.18 no.2
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• pp.65-73
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• 2008

Security layer of the Cdma2000 1x EV-DO is currently completing standard (C.S0024-A v2.0). Accordingly, a hardware security devices, that allows to implementation requirement of the security layer described in standard document, is required to apply security function about data transferred between AT and AN of then Cdma2000 1x EV-DO environment. This paper represents design of hardware device providing EV-DO security with simulation of the security layer protocol via the FPGA platform. The SHA-1 hash algorithm for certification and service of packet data, and the AES, SEED, ARIA algorithms for data encryption are equip in this device. And paper represents implementation of hardware that applies optionally certification and encryption function after executing key-switch using key-switching algorithm.

• Journal of the Korea Society for Simulation
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• v.25 no.4
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• pp.43-52
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• 2016

Wireless sensor network (WSN) technology has been implemented using commercial off-the-shelf microcontrollers (MCUs), In this paper, we propose a simulation environment to realize the physical evaluation of FPGA-based node by considering vertically cross-layered WSN in terms of physical node device and network interconnection perspective. The proposed simulation framework emulates the physical FPGA-based sensor nodes to interoperate with the NS3 through the runtime infrastructure (RTI). For the emulation and interoperation of FPGA-based nodes, we extend a vendor-providing FPGA design tool from the host computer and a script to execute the interoperation procedures. The standalone NS-3 is also revised to perform interoperation through the RTI. To resolve the different time-advance mechanisms between the FPGA emulation and event-driven NS3 simulation, the pre-simulation technique is applied to the proposed environment. The proposed environment is applied to IEEE 802.15.4-based low-rate, wireless personal area network communication.

• Proceedings of the Acoustical Society of Korea Conference
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• 1998.06c
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• pp.347-350
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• 1998

최근 개인 휴대통신과 컴퓨터 기술의 발달로 유용한 데이터의 질적.양적 향상을 가져왔다. 이로 인해 저장중이거나 선로상에서의 전송중인 정보의 보호문제가 중요시되고 있다. 이러한 정보보호 문제가 중요시됨에 따라 정보보호를 위한 직접적인 암호화 방법중의 하나인 IDEA(International Data Encryption Algorithm)의 구현을 제안하고자 한다. IDEA는 블록 암호화 방식의 하나로서 64비트 데이터를 암호화하기 위해 128비트의 키를 사용한다. 본 논문에서 암호알고리즘 구현을 위하여 하드웨어 설계언어인 VHDL을 사용하였고, V-System을 이용하여 Simulation을 수행하였다. Coding된 알고리즘은 Synopsy를 사용하여 자동합성하였고, Xilinx사의 FPGA-4025를 Target으로 구현하였다.

• Proceedings of the KIEE Conference
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• 2001.11c
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• pp.383-386
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• 2001

본 논문에서는 전력과 대역특이 제한된 환경에서 효율적인 트렐리스 부호화 변조방식을 적용한 QAM 모뎀을 구현하였다. 입력되는 데이터를 트렐리스 부호화 변조한 후 I, Q로 분리된 신호는 신호 사상기를 통하여 해당하는 성 상점으로 변환된다. 복조기는 I, Q의 신호를 트렐리스 복호기에 입력하여 데이터를 복구한다. 변복조기의 구현은 Xilinx사의 FPGA 디자인툴인 Foundation을 사용하여 VHDL simulation과 Chip Targeting을 수행하였다.

• Proceedings of the Korea Information Processing Society Conference
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• 2005.11a
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• pp.727-730
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• 2005

최근 로봇에 대한 연구가 활발히 진행되면서 로봇이 움직이면서 필요한 거리정보를 얻기 위한 여러 가지 3D Sensing 알고리즘이 제시되었다. 그 중 하나인 HOC(hierarchical orthogonal code) 알고리즘 이용하면서 실시간성 및 모듈화를 위해 CIS(CMOS Image Sensor), FPGA 를 이용하여 구현 하였다.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.7 no.1
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• pp.33-44
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• 1997

BISDN(Broadband Integrated Service Digital Network)의 AAL-1(ATM Adaptation Layer-1)에서는 오류정정능력이 2인 (128,124) RS(Reed Slomon) 부호를 이용하여 ATM 셀에서 발생하는 오류를 정정하고 있다. 본 논문에서는 기존의 RS 복호 알고리즘을 분석한 후, 이를 바탕으로 AAL-1 기본오류정정 모드에 적용 가능한 복잡도가 낮고 고속 동작이 가능한 복호 알고리즘을 제시하고, 부호기와 보호기를 VHDL로 부호화하고 설계한 후, 관련 회로를 시뮬레이션한다. 또한 시뮬레이션된 회로를 XACT을 이용하여 XC 4025 FPGA에 실현하여 제안되 복호 알고리즘의 타당성을 확인한다.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.813-816
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• 2005

In last several years, the need for the right of privacy and mobile banking has increased. The RSA system is one of the most widely used public key cryptography systems, and its core arithmetic operation IS modular multiplication. P. L. Montgomery proposed a very efficient modular multiplication technique that is well suited to hardware implementation. In this paper, the montgomery modular multiplication algorithms(CIOS, SOS, FIOS) , developed by Cetin Kaya Koc, is presented and implemented using radix-16 and Altera FPGA. Also, we undertake comparisons of power dissipation using Quatrus II PowerPlay Power Analyzer.