• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.5
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• pp.1089-1094
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• 2013

In this study, we propose how th implement a MDDI(Mobile Display Digital Interface) protocol packet generation method in software. MDDI protocol is widely used in mobile display device. MDDI protocol packets are generated by software within micro processor. This method needs the minimum hardware configuration. In order to implementation of this method, we design a hardware platform with a high performance microprocessor and a FPGA. The packets generated by software within microprocessor are converted into LVDS signals, and transmitted by hardware within FPGA. This study suggests the benefits of the way how software can easily create a variety of packet. But, this proposed method takes more time in packet transmission compared to the traditional method. This weakness remains as a future challenge, which can be soon improved.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.40 no.5
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• pp.332-346
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• 2003

In this paper, a system which can compress and reconstruct the digital image was implemented using 2 dimensional DWT(Discrete Wavelet Transform). The proposed system consists of the FPGA board tocompress the image and the application software(S/W) to reconstruct it. First the FPGA receives the image from AID converter and compresses the image using wavelet transform. The compressed data is transferred into the PC using the PCI interface. The compressed image is reconstructed by an application S/W inside the PC. The image compressor can compress about 60 fields per second, in which the image format was NTSC YCbCr(4:2:2) and the image size was 640${\times}$240 pixels per field. The designed hardware mapped into one FPGA occupying 11,120 LAB (Logic Array Block) and 27,456 ESB(Embedded System Block) in APEX20KC EP20K1000B652-7. It globally uses 33MHz clock and the memory control part uses 100MHz.

• Journal of the Institute of Convergence Signal Processing
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• v.12 no.4
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• pp.315-321
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• 2011

The CRT monitor display system for SONAR signal that are commonly used in ships or naval vessels uses vector scanning method. Therefore the processing circuits of the system is complex. Also because production had been shut down, the supply of parts is difficult as well as high-cost. FPGA -based embedded processor system is flexible to adapting to various applications because it makes simple processing circuits and its core is easily reconfigurable, and provides high speed performance in low-cost. In this paper, we describe an implementation of SONAR signal LCD display system using the FPGA embedded processor system to overcome some weakness of existing CRT system. By changing X-Y Deflection and CRT control blocks of current system into FPGA embedded processor system, our system provides the simplicity, flexibility and low-cost of system configuration, and also real-time acquisition and display of SONAR signal.

• The Transactions of the Korean Institute of Power Electronics
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• v.12 no.4
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• pp.339-345
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• 2007

This paper presents a design of an FPGA (Field Programmable Gate Array) -based currentcontroller. Using the nature of the high computational capability of FPGA, the digital delay due to the algorithm execution can be reduced. The control performance can be better than the conventional DSP (Digital Signal Processor)-based current controller. Moreover, this method does not need any delay compensation algorithm because the digital delay is physically diminished. Therefore, the bandwidth of the current controller can be extended by this method. The feasibility of this method is verified by several experimental results under the various conditions.

• Journal of Power Electronics
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• v.16 no.2
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• pp.553-563
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• 2016

This paper presents a digital hardware implementation of a real-time simulator for a multiphase drive using a field-programmable gate array (FPGA) device. The simulator was developed with a modular and hierarchical design using very high-speed integrated circuit hardware description language (VHDL). Hence, this simulator is flexible and portable. A state-space representation model suitable for FPGA implementations was proposed for a dual three-phase induction machine (DTPIM). The simulator also models a two-level 12-pulse insulated-gate bipolar transistor (IGBT)-based voltage-source converter (VSC), a pulse-width modulation scheme, and a measurement system. Real-time simulation outputs (stator currents and rotor speed) were validated under steady-state and transient conditions using as reference an experimental test bench based on a DTPIM with 15 kW-rated power. The accuracy of the proposed digital hardware implementation was evaluated according to the simulation and experimental results. Finally, statistical performance parameters were provided to analyze the efficiency of the proposed DTPIM hardware implementation method.

• IEIE Transactions on Smart Processing and Computing
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• v.4 no.4
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• pp.237-250
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• 2015

This paper describes a hardware-oriented algorithm and its conceptual implementation in a real-time speed limit traffic sign detection system on an automotive-oriented field-programmable gate array (FPGA). It solves the training and color dependence problems found in other research, which saw reduced recognition accuracy under unlearned conditions when color has changed. The algorithm is applicable to various platforms, such as color or grayscale cameras, high-resolution (4K) or low-resolution (VGA) cameras, and high-end or low-end FPGAs. It is also robust under various conditions, such as daytime, night time, and on rainy nights, and is adaptable to various countries' speed limit traffic sign systems. The speed limit traffic sign candidates on each grayscale video frame are detected through two simple computational stages using global luminosity and local pixel direction. Pipeline implementation using results-sharing on overlap, application of a RAM-based shift register, and optimization of scan window sizes results in a small but high-performance implementation. The proposed system matches the processing speed requirement for a 60 fps system. The speed limit traffic sign recognition system achieves better than 98% accuracy in detection and recognition, even under difficult conditions such as rainy nights, and is implementable on the low-end, low-cost Xilinx Zynq automotive Z7020 FPGA.

• Proceedings of the IEEK Conference
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• 2001.06d
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• pp.191-194
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• 2001

This paper presents a real-time implementation method of a laser pointer mouse system. This system consists of a camera, a FPGA circuits to track a laser footprint and RF module for communication between a laser pointer and the proposed system. We first simulate the system and realize the system by a FPGA circuit after implementing it by a VHDL.

• Proceedings of the Korean Information Science Society Conference
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• 2004.04a
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• pp.934-936
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• 2004

본 논문의 목적은 AES(Advanced Encryption Standard)로 선정된 Rijndael 암호 및 복호 알고리즘을 하드웨어로 설계하고 이를 저비용의 FPGA로 구현하는 것이다. 설계된 AES 암호프로세서는 20만 게이트 급 이하의 FPGA로 구현한다는 비용의 제약 조건 하에서 대용량의 데이터를 암호화, 복호화 하기에 적합한 성능을 가지도록 하였다. 또한 구현 단계에서는 설계한 AES 암호프로세서와 UART 모듈을 동일 FPGA상에서 통합하여 실용성 및 면적 효율성을 보였다. 구현된 Rijndael 암호 프로세서는 20만 게이트를 갖는 Xilinx사의 Spartan-II 계열의 XC2S200 칩 사용시 53%의 면적을 차지하였고, Static Timing Analyzer로 분석한 결과 최대 29.3MHz 클럭에서 동작할 수 있고 337Mbps의 최대 성능을 가진다. 구현된 회로는 실제 FPGA를 이용하여 검증을 수행하였다.

• Proceedings of the IEEK Conference
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• 2003.07e
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• pp.1787-1790
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• 2003

In this paper. we proposed a hardware(H/W) structure which can compress the video and embed the watermark in real time operation and implemented it into a FPGA platform using VHDL(VHSIC Hardware Description Language). All the image processing element to process both compression and reconstruction in a FPGA were considered each of them was mapped into H/W with the efficient structure for FPGA. The global operations of the designed H/W consists of the image compression with the watermarking and the reconstruction, and the watermarking operation is concurrently operated with the image compression. The implemented H/W used the 59％(12943) LAB(Logic Array Block) and 9％(28352) ESB(Embedded System Block) in the APEX20KC EP20K600CB652-7 FPGA chip of ALTERA, and stably operated in the 70㎒ clock frequency over. So we verified the real time operation, 60 fields/sec(30 frames/sec).

• IEMEK Journal of Embedded Systems and Applications
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• v.10 no.6
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• pp.363-372
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• 2015

Recent some SoC FPGA Releases that integrate ARM processor and FPGA fabric show better performance compared to the ASIC SoC used in typical embedded image processing system. In this study, using the above advantages, we implement a SoC FPGA-based Real-Time Object Recognition and Tracking System. In our system, the video input and output, image preprocessing process, and background subtraction processing were implemented in FPGA logics. And the object recognition and tracking processes were implemented in ARM processor-based programs. Our system provides the processing performance of 5.3 fps for the SVGA video input. This is about 79 times faster processing power than software approach based on the Nios II Soft-core processor, and about 4 times faster than approach based the HPS processor. Consequently, if the object recognition and tracking system takes a design structure combined with the FPGA logic and HPS processor-based processes of recent SoC FPGA Releases, then the real-time processing is possible because the processing speed is improved than the system that be handled only by the software approach.