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Image Compression System Implementation Based on DWT  

서영호 (광운대학교 전자재료공학과)
최순영 (광운대학교 전자재료공학과)
김동욱 (광운대학교 전자재료공학과)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SP / v.40, no.5, 2003 , pp. 332-346 More about this Journal
Abstract
In this paper, a system which can compress and reconstruct the digital image was implemented using 2 dimensional DWT(Discrete Wavelet Transform). The proposed system consists of the FPGA board tocompress the image and the application software(S/W) to reconstruct it. First the FPGA receives the image from AID converter and compresses the image using wavelet transform. The compressed data is transferred into the PC using the PCI interface. The compressed image is reconstructed by an application S/W inside the PC. The image compressor can compress about 60 fields per second, in which the image format was NTSC YCbCr(4:2:2) and the image size was 640${\times}$240 pixels per field. The designed hardware mapped into one FPGA occupying 11,120 LAB (Logic Array Block) and 27,456 ESB(Embedded System Block) in APEX20KC EP20K1000B652-7. It globally uses 33MHz clock and the memory control part uses 100MHz.
Keywords
DWT; FPGA; Image Compression; Hardware Implementation;
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