• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.10a
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• pp.336-339
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• 2007

A chaos signal is used in all fields like engineering, a medical science and a biology very much, and study regarding the digital communication system that used a recent chaos signal is consisting actively. Applied a chaos signal in a digital communication system, and this paper designed six chaos signal generator to have been composed of by nonlinear equations as used System Generator, and implemented hardware to FPGA. Loaded bit stream to a FPGA board in order to verify this design to Hardware co-simulation from these results. Also, compared as investigated the maximum action frequency through timing analysis and resource of logic in order to evaluate performance of six chaos generator.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2013.05a
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• pp.723-724
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• 2013

• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.575-580
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• 2003

In this paper, we develop a control hardware such as an FPGA based general purpose controller with a DSP board to solve nonlinear control problems. PID control algorithms are implemented in an FPGA and neural network control algorithms are implemented in a DSP board. PID controllers implemented on an FPGA was designed by using VHDL to achieve high performance and flexibility. By using high capacity of an FPGA, the additional hardware such as an encoder counter and a PWM generator, can be implemented in a single FPGA device. As a result, the noise and power dissipation problems can be minimized and the cost effectiveness can be achieved. In order to show the performance of the developed controller, it was tested for controlling nonlinear systems such as an inverted pendulum.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.10a
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• pp.675-676
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• 2012

In this paper, we are implemented the signal measurement system based on FPGA. The proposed hardware was mapped into Cyclone III from Altera and used 1,700(40%) of Logic Element (LE). The implemented circuit used 24,576-bit memory element with 6-bit input signal. The result from implementing in hardware (FPGA) could operate stably in 140MHz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.1
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• pp.20-27
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• 2008

In this paper, a nonlinear classifier of a feed-forward neural network is implemented on an FPGA chip. The feedforward neural network is implemented in hardware for fast parallel processing. After off line training of neural network, weight values are saved and used to perform forward propagation of neural processing. As an example, AND and XOR digital logic classification is conducted in off line, and then weight values are used in neural network. Experiments are conducted successfully and confirmed that the FPGA neural network hardware works well.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.05a
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• pp.167-169
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• 2010

This paper describes hardware design and FPGA verification of TFT-LCD controller used in mobile devices widely. TFT-LCD controller outputs pixel's color information red, green, blue and Hsync, Vsync synchronization signals. We used verilog-hdl to describe TFT-LCD controller and simulated it using modelsim software and verified it's exact operation on Xilinx FPGA. Framebuffer made up Block RAM form in FPGA and TFT-LCD displayed image file.

• The Journal of the Korea institute of electronic communication sciences
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• v.8 no.11
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• pp.1707-1712
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• 2013

In this paper, we implement a hardware for motor control based on FPGA + embedded processor using Zynq EPP which is All Programmable SoC in order to improve a structural problem of motion control based on such as DSP, MCU and FPGA previously. The implemented motor controller that is fused controller with advantage of FPGA and embedded processor. The signal processing part of high velocity motor control is performed by motor controller based on FPGA. A motion profile and kinematic calculation that are required algorithm process such as operation of a complicate decimal point has processed in an embedded processor based on dual core. As a result of a hardware implementation, it has an advantage that has can be realized an effect of distribution process in one chip. It has also an advantage that is able to organize as a multi-axis motor controller through adding the IP core of motor control implemented on FPGA.

• Journal of IKEEE
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• v.25 no.1
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• pp.10-14
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• 2021

This paper presents a hardware that improves the complexity of the CIE1931 color coordinate algorithm operation. The conventional algorithm has disadvantage of growing hardware due to 4-Split Multiply operations used to calculate large bits in the computation process. But the proposed algorithm pre-calculates the defined R2X, X2R Matrix operations of the conventional algorithm and makes them a matrix. By applying the matrix to the images and improving the color, it is possible to reduce the amount of computation and hardware size. By comparing the results of Xilinx synthesis of hardware designed with Verilog, we can check the performance for real-time processing in 4K environments with reduced hardware resources. Furthermore, this paper validates the hardware mount behavior by presenting the execution results of the FPGA board.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.3A
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• pp.185-196
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• 2009

SCA is proposed in order to operate various wireless systems in the single terminal platforms and uses the CORBA middleware to guarantee the platform-independence for software components. As the reconstruction demand is expanded in the software component to the logic level to many reasons, CORBA has to guarantee the independence of hardware on board. Accordingly. the characteristics depending on hardware board is ed. And the IDL-based interworking interface about the component has to be provided. In this paper, we described about local transport for guaranteeing the independency on the hardware board and the HAO Core for providing a coupling by the CORBA IDL identically with the other component. HAO produced at 2,900 logic cell size in average and provided the performance of the tens times than the software component. Through the use of HAO in the SCA-based development environment, it was naturally expanded to not only the software area but also the FPGA logic.

• Journal of IKEEE
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• v.22 no.3
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• pp.578-584
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• 2018

Image segmentation has been presented in the various method in image interpretation and recognition, and the image is using separate the characteristics of the specific purpose. In this paper, we proposed an algorithm that separate image for feature points detected to high temperature in a Thermal infrared image. In order to improve the processing time, the proposed algorithm is implemented to FPGA Hardware Block using the Zynq-7000 Evaluation Board environment. The proposed High-Temperature Detection Algorithm and total FPGA blocks show a decrease of a processing time result from 16ms to 0.001ms, and from 50ms to 0.322ms respectively. It is also verified similar results of the PSNR to comparing software thermal testbench and hardware ones.