• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.3C
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• pp.306-313
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• 2007

In this paper, we efficiently implemented turbo code algorithm in FPGA H/W(hardware) resource. The used turbo code algorithm has the characteristics; the size of constraint is 3, encoder type is 1/3, the size of random interleaver is 2048. The proposed H/W consists of MAP block for calculating alpha and delta using delta value, storing buffer for each value, multiplier for calculating lamda, and lamda buffer. The proposed algorithm and H/W architecture was verified by C++ language and was designed by VHDL. Finally the designed H/W was programmed into FPGA and tested in wireless communication environment for field availability. The target FPGA of the implemented H/W is VERTEX4 XC4VFX12-12-SF363 and it is stably operated in 131.533MHz clock frequency (7.603ns).

• The Journal of the Korea institute of electronic communication sciences
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• v.8 no.11
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• pp.1707-1712
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• 2013

In this paper, we implement a hardware for motor control based on FPGA + embedded processor using Zynq EPP which is All Programmable SoC in order to improve a structural problem of motion control based on such as DSP, MCU and FPGA previously. The implemented motor controller that is fused controller with advantage of FPGA and embedded processor. The signal processing part of high velocity motor control is performed by motor controller based on FPGA. A motion profile and kinematic calculation that are required algorithm process such as operation of a complicate decimal point has processed in an embedded processor based on dual core. As a result of a hardware implementation, it has an advantage that has can be realized an effect of distribution process in one chip. It has also an advantage that is able to organize as a multi-axis motor controller through adding the IP core of motor control implemented on FPGA.

• The Transactions of the Korean Institute of Power Electronics
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• v.11 no.2
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• pp.127-134
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• 2006

This paper describes a fully hardware realization of vector controller for the permanent magnet synchronous motor (PMSM) using high density field programmable gate mays (FPGA). In the proposed system, the vector controller including vector transformation , PI regulator, position and speed measurement, current measurement, and space vector PWM blocks is implemented in a FPGA using a VHSIC hardware description language (VHDL). The experimental results using a 1.1kW PMSM are provided to show the validity of the proposed system.

• The Journal of the Korea institute of electronic communication sciences
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• v.11 no.5
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• pp.465-472
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• 2016

This study materialized an FPGA-based system to extract PCB patterns. The Printed Circuit Boards that are produced these days are becoming more detailed and complex. Therefore, the importance of a vision system to extract defects of detailed patterns is increasing. This study produced an FPGA-based system that has high speed handling for vision automation of the PCB production process. A vision library that is used to extract defect patterns was also materialized in IPs to optimize the system. The IPs materialized are Camera Link IP, pattern matching IP, VGA IP, edge extraction IP, and memory IP.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.10a
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• pp.131-134
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• 2007

In this paper, we propose the 1D-CZP pattern for FPGA verification. The algorithm that was implemented by Verilog-HDL on FPGA board is verified before the chip is producted. Input through the external sensor might not be enough to verify the algorithm on FPGA board. Hence, both external input and internal input can lead the verification of the algorithm. This paper suggests the hardware implementation of compact 1D-CZP pattern that has the random input. It is useful to analyze the characteristics of the filter frequencies and organized as ROM Table which is efficient to Modulus operation.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.8
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• pp.1488-1494
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• 2008

This paper is to design and implement a low power noncoherent BFSK receiver intended for future deep space communication using Xilinx System generator. The receiver incorporates a 16 point Fast Fourier Transform(FFT) for symbol detection. The design units of the receiver are digital design for better efficiency and reliability. The receiver functions on one bit data processing and supports main data rate 10kbps. In addition CORDIC algorithm is used for avoiding complex multiplications while computing FFT and multiplication of twiddle factor for low power is substituted by rotators. The design and simulation of the receiver is carried out in Simulink then the Simulink model is translated to the hardware model to implement FPGA using Xilinx System Generator and to verify performance.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.17 no.5
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• pp.55-63
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• 2007

This paper has investigated the susceptibility of an FPGA implementation of a block cipher against side channel analysis attacks. We have performed DPA attacks and DEMA attacks (in the nea. and far field) on an FPGA implementation of ARIA which has been implemented into two architectures of S-box. Although the number of needed traces for a successful attack is increased when compared with existing results on smart cards, we have shown that ARIA without countermeasures is indeed very susceptible to side channel analysis attacks regardless of an architecture of S-box.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.23 no.5
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• pp.115-121
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• 2023

RISC-V is an open-source instruction set architecture, and anyone can freely design and implement a RISC-V microprocessor. This paper designes and simulates the RISC-V architecture, synthesizing it in FPGA and verifying it using logic analyzer (ILA). RISC-V core is written in SystemVerilog, which has efficient design and high reusability, and can be used in various application fields. The RISC-V core is implemented as hardware by synthesizing it on the Ultra96-V2 FPGA board using Vivado, and the accuracy and operation of the design are verified through Integrated Logic Analyzer(ILA). As a result of the experiment, it is confirmed that the designed RISC-V core performs the expected operation, and these results can contribute to the design and verification of RISC-V based systems.

• Proceedings of the KIEE Conference
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• 2000.07d
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• pp.2939-2941
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• 2000

FPGA는 ASIC설계의 시험을 위한 테스트용으로 많이 사용되었으나 최근에는 비약적인 성능 향상으로 그 자체로 기능을 구현하고 있다 퍼지 제어기의 구현은 일반적으로 범용 마이크로 프로세서를 이용하거나 DSP 프로세서를 이용하였다. 본 논문에서는 여러 퍼지 시스템 중에서 적은 규칙수로도 효과적인 성능을 나타내고 프로세서화가 용이한 TSK 퍼지 시스템을 구현한다. 대상 FPGA는 Xilinx사의 FPGA를 이용하고 Schematic과 VHDL을 혼용하여 설계한다 또한 구현된 프로세서의 범용성을 유지하기 위해 외부 ROM에서 연산에 필요한 계수를 취하는 방식을 채택 한다.

• Proceedings of the KIEE Conference
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• 2003.11c
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• pp.971-974
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• 2003

본 논문은 DC Motor의 속도 제어를 위해서는 속도를 결정해주는 PWM 출력과 Motor의 속도를 측정할 수 있는 고속카운터가 필요하며 설정한 값과 실제 출력되는 값을 동일하게 만들어주는 제어부분을 구현하여야 하며 시스템을 구성하기 위한 주변 I/O도 구성되어야 한다. 기존 마이크로프로세서로 구현을 하게 되면 PWM 출력과 제어 알고리즘에 대한 연산 및 주변 I/O에 대한 구현이 용이하겠지만 DC Motor의 Encoder에서 나오는 신호를 카운터하기에는 부족한 측면이 많으며 마이크로프로세서의 연산처리 과정에 따라 제어 알고리즘 연산에 소비되는 시간도 FPGA로 구현한 시스템보단 상대적으로 여유가 없다. 본 논문에서는 FPGA만을 이용하여 PWM, HSC, PID, 주변 I/O등을 하나의 Chip에 System On Chip화함으로 실제 시스템에 적용할 때 제어시스템의 소형화와 제어대상을 고속의 정확성있는 제어시스템을 연구 하였다.