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FPGA Design of Turbo Code based on MAP  

Seo, Young-Ho (한성대학교 정보통신공학과)
Publication Information
The Journal of Korean Institute of Communications and Information Sciences / v.32, no.3C, 2007 , pp. 306-313 More about this Journal
Abstract
In this paper, we efficiently implemented turbo code algorithm in FPGA H/W(hardware) resource. The used turbo code algorithm has the characteristics; the size of constraint is 3, encoder type is 1/3, the size of random interleaver is 2048. The proposed H/W consists of MAP block for calculating alpha and delta using delta value, storing buffer for each value, multiplier for calculating lamda, and lamda buffer. The proposed algorithm and H/W architecture was verified by C++ language and was designed by VHDL. Finally the designed H/W was programmed into FPGA and tested in wireless communication environment for field availability. The target FPGA of the implemented H/W is VERTEX4 XC4VFX12-12-SF363 and it is stably operated in 131.533MHz clock frequency (7.603ns).
Keywords
Turbo code; Ecc; FPGA; H/W; Communication;
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