• 대한전자공학회논문지
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• 제26권12호
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• pp.2010-2015
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• 1989

A SOI was fabricated by the FIPOS technique using n/p+/p silicon structure. Fabricated silicon island which has 3\ulcorner thickness and 100\ulcorner width was investigated by measuring van der Pauw resistivity, Hall mobility, dielectric breakdown voltage and leakage current. Hall mobility of the SOI was measured to be 300-500cm\ulcornerV.sec and its breakdown field was 1-2 MV/cm. The cross-sectional geometries of the SOI island were examined by SEM and optical microscope.

• ETRI Journal
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• 제9권1호
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• pp.146-157
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• 1987

SOI(Silicon-On-Insulator)는 차세대 VLSI 구조로서 최근 중요한 연구개발 대상이 되고 있다. SOI의 제조기술을 크게 recrystallization, ELO, FIPOS 및 SIMOX로 나누고 이들 각 기술에 대한 고찰을 하였다. 향후 전반적인 SOI 제조기술 개발방향은 SOI면적 확장 및 결함 감소를 위한 것이 될 것이다.

• 대한전자공학회논문지
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• 제25권11호
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• pp.1304-1314
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• 1988

Porous실리콘 形成反應에서 HF濃度, 電流應度, 反應時間 및 基叛의 表面狀態가 PSL (Porous Silicon Layers)의 porosity에 미치는 影響을 실험적으로 조사하였다. PSL을 陽배化 시켜서 室溫에서 FIPPOS-SOI를 제조하는 방법을 연구하였다. 이 방법으로 100um폭의 SOI strip line을 제조하였으며 SOI의 stress제거를 위해 2단계 PSL 형성법을 이용하였다. 또한 이 실온 SOI 제조기술을 이용하여 이미 소자공정을 끝낸 집적회로를 SOI화 시킬 수 있는 방법을 제안하였다.

• 한국재료학회지
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• 제15권9호
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• pp.613-619
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• 2005

The ever increasing popularity and acceptance in the market place of portable systems, such as cell phones, PDA, notebook PC, etc., are fueling effects in further miniaturizing and lowering power consumption in these systems. The dynamic power consumption due to the CPU activities and the static power consumption due to leakage currents are two major sources of power consumption. Smaller devices and a lower de voltage lead to reducing the power requirement, while better insulation and isolation of devices lead to reducing leakage currents. All these can be harnessed in the SOI (silicon-on-insulator) technology. In this study, the key aspects of the SOI technology, mainly device electrical properties and device processing steps, are briefly reviewed. The interesting materials issues, such as SOI structure formation and SOI wafer fabrication methods, are then surveyed. In particular, the recent technological innovations in two major SOI wafer fabrication methods, namely wafer bonding and SIMOX, are explored and compared in depth. The results of the study are nixed in that, although the quality of the SOI structures has shown great improvements, the processing steps are still found to be too complex. Between the two methods, no clear winner has yet emerged in terms of the product quality and cost considerations.