• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.12
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• pp.2010-2015
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• 1989

A SOI was fabricated by the FIPOS technique using n/p+/p silicon structure. Fabricated silicon island which has 3\ulcorner thickness and 100\ulcorner width was investigated by measuring van der Pauw resistivity, Hall mobility, dielectric breakdown voltage and leakage current. Hall mobility of the SOI was measured to be 300-500cm\ulcornerV.sec and its breakdown field was 1-2 MV/cm. The cross-sectional geometries of the SOI island were examined by SEM and optical microscope.

• ETRI Journal
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• v.9 no.1
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• pp.146-157
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• 1987

SOI(Silicon-On-Insulator)는 차세대 VLSI 구조로서 최근 중요한 연구개발 대상이 되고 있다. SOI의 제조기술을 크게 recrystallization, ELO, FIPOS 및 SIMOX로 나누고 이들 각 기술에 대한 고찰을 하였다. 향후 전반적인 SOI 제조기술 개발방향은 SOI면적 확장 및 결함 감소를 위한 것이 될 것이다.

• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.11
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• pp.1304-1314
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• 1988

An experimental study of the influences of HF concentration, current density, reaction time and the silicon surface, on the formation and properties of porous silicon are reported. The SOI (Silicon-On-Insulator) strip lines with 100 um width are fabricated at room temperature by anodic oxidation of PSL (Porous Silicon Layers). The stress on the silicon island induced by the anodic oxidation can be avoided by the two-step PSL formation technique. At the final step of IC fabrication process, device isolation will be achieved at room temperature by this method.

• Korean Journal of Materials Research
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• v.15 no.9
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• pp.613-619
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• 2005

The ever increasing popularity and acceptance in the market place of portable systems, such as cell phones, PDA, notebook PC, etc., are fueling effects in further miniaturizing and lowering power consumption in these systems. The dynamic power consumption due to the CPU activities and the static power consumption due to leakage currents are two major sources of power consumption. Smaller devices and a lower de voltage lead to reducing the power requirement, while better insulation and isolation of devices lead to reducing leakage currents. All these can be harnessed in the SOI (silicon-on-insulator) technology. In this study, the key aspects of the SOI technology, mainly device electrical properties and device processing steps, are briefly reviewed. The interesting materials issues, such as SOI structure formation and SOI wafer fabrication methods, are then surveyed. In particular, the recent technological innovations in two major SOI wafer fabrication methods, namely wafer bonding and SIMOX, are explored and compared in depth. The results of the study are nixed in that, although the quality of the SOI structures has shown great improvements, the processing steps are still found to be too complex. Between the two methods, no clear winner has yet emerged in terms of the product quality and cost considerations.