• Journal of Institute of Control, Robotics and Systems
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• v.20 no.1
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• pp.37-41
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• 2014

FFT (Fast Fourier Transform) has been widely used in various fields such as image processing, voice processing, physics, astronomy, applied mathematics and so forth. Much research has been conducted due to the importance of the FFT and recently new FFT algorithms using a GPU (Graphics Processing Unit) have been developed for the purpose of much faster processing. In this paper, the new optimal FFT algorithm using the Pease FFT algorithm has been proposed reflecting the hardware configuration of a GPGPU (General Purpose computing of GPU). According to the experiments, the proposed algorithm outperformed by between 3% to 43% compared to the CUFFT algorithm.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.34 no.1
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• pp.11-19
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• 2024

The increased utilization of the FFT in signal processing, cryptography, and various other fields has highlighted the importance of optimization. In this paper, we propose the implementation of an accelerator that processes the radix-2 16 points FFT algorithm more rapidly and efficiently than FFT implementation of existing studies, using FPGA(Field Programmable Gate Array) hardware. Leveraging the hardware advantages of FPGA, such as parallel processing and pipelining, we design and implement the FFT logic in the PL (Programmable Logic) part using the Verilog language. We implement the FFT using only the Zynq processor in the PS (Processing System) part, and compare the computation times of the implementation in the PL and PS part. Additionally, we demonstrate the efficiency of our implementation in terms of computation time and resource usage, in comparison with related works.

• Proceedings of the Korea Information Processing Society Conference
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• 2013.05a
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• pp.131-134
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• 2013

영상처리, 음성처리, 물리학, 천문학, 응용 수학등 다양한 분야에 FFT가 널리 사용되고 있다. FFT의 중요성 때문에 많은 연구가 이루어졌고, 최근 고속처리를 위하여 GPU를 활용한 FFT 알고리즘들이 개발되고 있다. 본 논문은 FFT알고리즘의 변형중 하나인 Pease FFT알고리즘을 GPGPU의 하드웨어 구성을 반영하여 최적화시킨 FFT 가속알고리즘을 제안한다. 실험결과 제안된 알고리즘은 CUFFT에 비하여 3% ~ 43%까지 우수한 성능을 보였다.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.2
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• pp.97-105
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• 2015

This paper discusses the implementation of Bruun's FFT on a SIMD processor. FFT is an algorithm used in digital signal processing area and its effective processing is important in the enhancement of signal processing performance. Bruun's FFT algorithm is one of fast Fourier transform algorithms based on recursive factorization. Compared to popular Cooley-Tukey algorithm, it is advantageous in computations because most of its operations are based on real number multiplications instead of complex ones. However it shows more complicated data alignment patterns and requires a larger memory for storing coefficient data in its implementation on a SIMD processor. According to our experiment result, in the processing of the FFT with 1024 complex input data on a SIMD processor, The Bruun's algorithm shows approximately 1.2 times higher throughput but uses approximately 4 times more memory (20 Kbyte) than the Cooley-Tukey algorithm. Therefore, in the case with loose constraints on silicon area, the Bruun's algorithm is proper for the processing of FFT on a SIMD processor.

• Speech Sciences
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• v.10 no.2
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• pp.57-64
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• 2003

The cepstrum coefficients are the most popular feature for speech recognition or speaker recognition. The cepstrum coefficients are also used for speech synthesis and speech coding but has major drawback of long processing time. In this paper, we proposed a new method that can reduce the processing time of FFT cepstrum analysis. We use the normal ordered inputs for FFT function and the bit-reversed inputs for IFFT function. Therefore we can omit the bit-reversing process and reduce the processing time of FFT ceptrum analysis.

• 한국정보통신설비학회:학술대회논문집
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• 2008.08a
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• pp.257-261
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• 2008

The Digital Radio Mondiale (DRM) system is a digital broadcasting standard designed for use in the LF, MF and HF bands of the broadcasting bands below 30 MHz. The system provides both superior audio quality and improved user services / operability compared with existing AM transmissions. In this paper, we propose a variable point Prime Factor FFT design method for Digital Radio Mondiale (DRM) system. Proposed method processes a various size IFFT/FFT of Robustness Mode on DRM standard efficiently by composing Radix-Prime Factor FFT Processing Unit of form similar to Radix-4 by insertion of a variable Prime Factor Twiddle Factor and Garbage data. So, we improved limitation that cannot process 112/176/256/288 FFT of each mode of DRM system with a existent Radix Processor and increase memory size and memory access time for IFFT/FFT processing by software processing in case of implementation with a existent high speed DSP.

• Journal of IKEEE
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• v.25 no.4
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• pp.697-702
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• 2021

Fast Fourier Transform (FFT) is a major signal processing block being widely used. For long-point FFT processing, usually more than 1024 points, its low-complexity implementation becomes very important while retaining high SQNR (Signal-to-Quantization Noise Ratio). In this paper, we present a low-complexity FFT algorithm with a simple dynamic scaling scheme. For the 2048-point pipelined FFT processing, we can reduce the number of general multipliers by half compared to the well-known radix-2 algorithm. Also, the table size for twiddle factors is reduced to 35% and 53% compared to the radix-2 and radix-2² algorithms respectively, while achieving SQNR of more than 55dB without increasing the internal wordlength progressively.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.3
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• pp.114-129
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• 1993

A FFT array processor algorithm and architecture which anc use a minumum required number of simple, duplicate multiplier-adder processing elements according to various computation speed, will be presented. It is based on the p fold symmetry in the radix p constant geometry FFT butterfly stage with shuffled inputs and normally ordered outputs. Also, a methodology to implement a high performance high radix FFT with VLSI by constructing a high radix processing element with the duplications of a simple lower radix processing element will be discussed. Various performances and the trade-off between computation speed and hardware complexity will be evaluated and compared. Bases on the presented architecture, a radix 2, 8 point FFT processing element chip has been designed and it structure and the results will be discusses.

• Proceedings of the Korea Information Processing Society Conference
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• 2008.05a
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• pp.1029-1030
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• 2008

FFT(Fast Fourier Transform)는 디지털신호처리에 폭넓게 사용되며 특히 여러 OFDM 시스템에 FFT 처리 과정은 꼭 필요한 부분이다. 본 논문에서는 802.11a W-LAN 에 사용되는 64-point FFT 프로세서를 설계하였다. 설계된 FFT 프로세서는 Radix-$2^3$ 알고리즘을 사용하였으며 저면적복소곱셈기를 사용하여 FFT 프로세서의 면적을 줄이는 방법을 제안한다. 기존의 방식에서 네 개의 실수 곱셈기와 두 개의 덧셈기로 구성되는 복소 곱셈기를 두 개의 실수 곱셈기와 한 개의 덧셈기가 수행하도록 설계하였다. 제안한 FFT 프로세서는 VHDL 로 구현되었고 Quartus 4.2 에서 합성되었다. 합성결과 기존 방식에 비해 약 21%의 면적효율이 발생하였다.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.8 no.4
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• pp.89-95
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• 2008

In the maritime communication, Orthogonal Frequency Division Multiplexing (OFDM) communication terminal should be operated with low power consumption, because the communication should be accomplished in the circumstance of disaster. Therefore, Low power FFT processor is required to be designed with current mode signal processing technique than digital signal processing. Current- to-Voltage Converter (IVC) is a device that converts the output current signal of FFT processor into the voltage signal. In order to lessen the power consumption of OFDM terminal, IVC should be designed with low power design technique and IVC should have wide linear region for avoiding distortion of signal voltage. To design of one-chip of the FFT LSI and IVC, IVC should have a small chip size. In this paper, we proposed the new IVC with wide linear region. We confirmed that the proposed IVC operates linearly within 0.85V to 1.4V as a function of current-mode FFT output range of -100~100[uA]. Designed IVC will contribute to realization of low-power maritime data communication using OFDM system.