• Journal of the Korean Society of Surveying, Geodesy, Photogrammetry and Cartography
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• v.14 no.1
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• pp.49-58
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• 1996

This paper deals with the gravimetric solution of geoid by Fast Fourier Transform(FFT) technique in and around Korean Peninsula. The used reference surface is OSU91A geopotential model up to degree and order 180 refered to GRS80. The remove and restore technique was applied to obtain the geoidal height in this paper. And the FFT with 20% window was applied to compute the medium wavelength effect from terrestrial gravity anomalies. For the comparison of computed results, the geometric geoidal height was derived from GPS/Levelling data. According to the comparison, the mean value and RMSE of the differences are 0.3819m and 0.4695m respectively.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.39 no.2
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• pp.1-10
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• 2002

This paper presents the new template based human face recognition methods to improve the recognition performance against scale and in-plane rotation variations of face images. To enhance the recognition performance, the templates are generated by linear or nonlinear operation on multiple images including different scales and rotations of faces. As the invariant features to allow for scale and rotation variations of face images, we adopt the affine transformation, the log-polar mapping, and the log-polar image based FFT. The proposed recognition methods are evaluated in terms of the recognition rate and the processing time. Experimental results show that the proposed template based methods lead to higher recognition rate than the single image based one. The affine transformation based face recognition method shows marginally higher recognition rate than those of the log-polar mapping based method and the log-polar image based FFT, while, in the aspect of processing time, the log-polar mapping based method is the fastest one.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.10
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• pp.2187-2193
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• 2010

A specific radar system can be implemented more easily using the frequency modulated continuous wave comparing with the pulse Doppler radar. It also has the advantage of LPI (low probability of interception) because of the low power and wide bandwidth characteristics. These radars are usually used to cover the short range area and to obtain the high resolution measurements of the target range and velocity information. The transmitted waveform is used in the mixer to demodulate the received echo signal and the resulting beat signal can be obtained. This beat signal is analyzed using the FFT method for the purpose of clutter removal, detection of a target, extraction of velocity and range information, etc. However, for the case of short signal acquisition time, this FFT method can cause the serious leakage effect which disables the detection of weaker echo signals masked by strong side lobes of the clutter. Therefore, in this paper, the weighting window method is analyzed to suppress the strong side lobes while maintaining the proper main lobe width. Also, the results of FFT beat spectrum analysis are shown under various environments.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.2
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• pp.97-105
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• 2015

This paper discusses the implementation of Bruun's FFT on a SIMD processor. FFT is an algorithm used in digital signal processing area and its effective processing is important in the enhancement of signal processing performance. Bruun's FFT algorithm is one of fast Fourier transform algorithms based on recursive factorization. Compared to popular Cooley-Tukey algorithm, it is advantageous in computations because most of its operations are based on real number multiplications instead of complex ones. However it shows more complicated data alignment patterns and requires a larger memory for storing coefficient data in its implementation on a SIMD processor. According to our experiment result, in the processing of the FFT with 1024 complex input data on a SIMD processor, The Bruun's algorithm shows approximately 1.2 times higher throughput but uses approximately 4 times more memory (20 Kbyte) than the Cooley-Tukey algorithm. Therefore, in the case with loose constraints on silicon area, the Bruun's algorithm is proper for the processing of FFT on a SIMD processor.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 2007.04a
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• pp.477-480
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• 2007

저전력 OFDM(orthogonal frequency division multiplexing) 시스템용 FFT(Fast-Fourier-Transform) LSI를 저전력 동작을 시키기 위해서 FFT LSI는 current-mode 회로로 구현되었다. Current-mode FFT LSI에서, VIC(Voltage-to-current converter)는 입력 전압 신호를 전류로 바꾸는 first main device이다. 저전력 OFDM을 위해 FFT LSI와 VIC가 한 개의 칩과 결합되는 것을 고려하면, VIC는 전력 손실은 낮고, VIC와 FFT LSI 사이에서의 DC offset 전류는 최소인 작은 크기의 chip으로 설계되어야 한다. 본 논문에서는 새로운 VIC를 제안한다. 선형 동작구간을 넓히고 DC offset 전류를 대폭 감소하는 방법을 제시하였다. VIC는 0.35[um] CMOS process로 구현되었으며, 시뮬레이션 결과에 따르면 제안된 VIC는 current-mode FFT LSI와 0.1[uA] 미만의 매우 작은 DC offset 전류, 1.4[V]의 넓은 선형구간을 갖으며, 저전력으로 동작한다.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2020.07a
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• pp.567-570
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• 2020

본 논문에서는 폴리곤기반 CGH 생성에서 텍스쳐 적용을 위한 준해석적 기법을 소개한다. 각각의 단위 폴리곤의 근방에서 폴리곤에 의해 회절되는 파면을 서로 독립인 기하학적 필드와 텍스쳐 필드의 곱으로 표현한다. 기하학적 필드는 기존의 해석적 방법을 적용하고 텍스쳐필드는 FFT 기반의 비해석적 방법을 적용하여 폴리곤 근방에서의 각스펙트럼을 얻고 이들의 FFT기반 합성곱을 통해 폴리곤 근방의 텍스쳐가 포함된 폴리곤의 회절 파면을 얻고 이를 홀로그램 평면까지 진행시켜 최종 홀로그램을 생성한다. 본 방법은 기하학적 필드에 해석적 방법을 적용하여 FFT기반의 비해석적 방법에 비해 복원 영상의 품질이 우수하며 CGH 생성속도 측면에서는 텍스쳐가 없는 경우의 해석적 방법과 유사하며 텍스쳐 이미지의 해상도에 상관없이 홀로그램 해상도에만 의존하는 장점이 있다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.5
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• pp.32-38
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• 2009

FTT(Fast Fourier Transform) processor is widely used in OFDM(Orthogonal Frequency Division Multiplesing) system. Because of the increased requirement of mobility and bandwidth in the OFDM system, they need large point FTT processor. Since the size of memory which stores the twiddle factor coefficients are proportional to the N of FFT size, we propose a new method by which we can reduce the size of the coefficient memory. In the proposed method, we exploit a counter and unsigned multiplier to generate the twiddle factor indices. To verify the proposed algorithm, we design TFCGs(Twiddle Factor Coefficient Generator) for 1024pint FFTs with R2SDF(Radix-2 Single-Path Delay Feedback), $R2^3SDF,\;R2^3SDF,\;R2^4SDF$ architectures. The size of ROM is reduced to 1/8N. In the case of $R2^4SDF$ architecture, the area and the power are reduced by 57.9%, 57.5% respectively.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.47 no.5
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• pp.100-108
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• 2010

An autocorrelation method is used in pitch estimation. Autocorrelation values in time and frequency domains, which have different characteristics, correspond to the pitch period and fundamental frequency, respectively. We utilize an integrated autocorrelation method in time and frequency domains. It can remove the errors of pitch doubling and having. In the time and frequency domains, pitch period and fundamental frequency have reciprocal relation to each other. Especially, fundamental frequency estimation ends up as an error because of the resolution of FFT. To reduce these artifacts, interpolation methods are applied in the integrated autocorrelation domain, which decreases pitch errors. Moreover, only for the pitch candidates found in a time domain, the corresponding frequency-domain autocorrelation values are calculated with reduced computational complexity. Using linear interpolation, we can decrease the required number of FFT coefficients by 8 times. Thus, compared to the conventional methods, computational complexity can be reduced by 9.5 times.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.47 no.10
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• pp.36-42
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• 2010

FFT(Fast Fourier Transform) processor is one of the key components in the implementation of OFDM systems for many wireless standards such as IEEE 802.22. To improve the performances of FFT processors, various studies have been carried out to reduce the complexities of multipliers, memory interface, control schemes and so on. While the number of FFT stages increases logarithmically $log_2N$) as the FFT point-size (N) increases, the number of required registers (or, memories) increases linearly. In large point-size FFT designs, the registers occupy more than 70% of the chip area. In this paper, to reduce the memory size of IFFT for OFDM transmitters, we propose a new IFFT design method based on a combined mapping of modulated data, pilot and null signals. The proposed method focuses on reducing the sizes of the registers in the first two stages of the IFFT architectures since the first two stages require 75% of the total registers. By simulations of 2048-point IFFT design for cognitive radio systems, it is shown that the proposed IFFT design method achieves more than 38.5% area reduction compared with previous IFFT designs.

• The Transactions of the Korean Institute of Power Electronics
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• v.13 no.3
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• pp.206-212
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• 2008

This paper proposes the PLL(Phase-Locked Loop) algorithm by a new FFT(Fast Fourier Transform) in a grid-connected PV PCS(Photovoltaics Power Conditionning System). The grid-connected inverter that is applied in a new renewable energy field needs the grid phase information for synchronism. Unlike the PLL which is normally used by three phase D-Q conversion, the preposed PLL algorithm using FFT has non-gain tuning and the powerful noise elimination by the characteristics of FFT. Both simulation and experimental result show that proposed algorithm has the good capacity.