• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.4
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• pp.35-42
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• 2013

In this paper, the analog performance of FinFET structure was estimated by extracting the DC/AC characteristics of the 22 nm process FinFET structures with different layout considering spacer and SEG using 3D device simulator, Sentaurus. Based on the analysis results, layout methods to enhance the analog performance of multi-fin FinFET structures are proposed. By adding the spacer and SEG structures, the drive current of 1-fin FinFET increases. However, the unity gain frequency, $f_T$, reduces by 19.4 % due to the increase in the total capacitance caused by the added spacer. If the process element is not included in multi-fin FinFET, replacing 1-finger with 2-finger structure brings approximately 10 % of analog performance improvement. Considering the process factors, we propose methods to maximize the analog performance by optimizing the interconnect and gate structures.

• Journal of the Semiconductor & Display Technology
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• v.14 no.2
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• pp.41-45
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• 2015

From 20nm technology node, the finFET has become standard device for ULSI's. However, the finFET process made stacking gate non-volatile memory obsolete. Some reported capacitor-less DRAM structure by utilizing the FBE. We present possible non-volatile memory device structure similar to the dual gate MOSFET. One of the gates is left floating. Since body of the finFET is only 40nm thick, control gate bias can make electron tunneling through the floating gate oxide which sits across the body. For programming, gate is biased to accumulation mode with few volts. Simulation results show that the programming electron current flows at the interface between floating gate oxide and the body. It also shows that the magnitude of the programming current can be easily controlled by the drain voltage. Injected electrons at the floating gate act similar to the body bias which changes the threshold voltage of the device.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2022.05a
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• pp.560-561
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• 2022

In this paper, current-voltage characteristics of various types of Nanosheet FET (NSFET) and FinFET are simulated with 3D device simulator. The threshold voltage and subthreshold swing extracted from the simulated current-voltage characteristics of NSFET and FinFET were compared. Both of threshold voltage and drain current of NSFET are higher than those of FinFET. The subthreshold voltage swing (SS) of NSFET is steeper than that of FinFET.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.4
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• pp.302-310
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• 2008

This paper puts forward an advanced consideration on the design of scaled multiple-gate FET (MuGFET); the aspect ratio ($R_{h/w}$) of the fin height (h) to fin width (w) of MuGFET is considered with the aid of 3-D device simulations. Since any change in the aspect ratio must consider the trade-off between drivability and short-channel effects, it is shown that optimization of the aspect ratio is essential in designing MuGFET's. It is clearly seen that the triple-gate (TG) FET is superior to the conventional FinFET from the viewpoints of drivability and short-channel effects as was to be expected. It can be concluded that the guideline of w < L/3, where L is the channel length, is essential to suppress the short-channel effects of TG-FET.

• Journal of information and communication convergence engineering
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• v.13 no.4
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• pp.257-263
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• 2015

In this study, organic field-effect transistors (OFETs) using a copper phthalocyanine (CuPc) material as an active layer and SiO₂ as a gate insulator were fabricated with varying active layer thicknesses and channel lengths. Further, using a thermal evaporation method in a high-vacuum system, we fabricated a CuPc FET device of the top-contact type and used Au materials for the source and drain electrodes. In order to discuss the channel formation and FET characteristics, we observed the typical current-voltage characteristics and calculated the threshold voltage of the CuPc FET device. We also found that the capacitance reached approximately 97 pF at a negative applied voltage and increased upon the accumulation of carriers at the interface of the metal and the CuPc material. We observed the typical behavior of a FET when used as an n-channel FET. Moreover, we calculated the threshold voltage to be about 15-20 V at V_DS = -80 V.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.653-653
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• 2013

In this study, ITO extended gate reduced graphene oxide field effect transistor (rGO FET) was demonstrated as a transducer for a proton sensing application. In this structure, the sensing area is isolated from the active area of the device. Therefore, it is easy to deposit or modify the sensing area without affecting on the device performance. In this case, the ITO extended gate was used as a gate electrode as well as a proton sensing material. The proton sensing properties based on the rGO FET transducer were analyzed. The rGO FET device showed a high stability in the air ambient with a TTC encapsulation layer for months. The device showed an ambipolar characteristic with the Dirac point shift with varying the pH solutions. The sensing characteristics have offered the potential for the ion sensing application.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.6
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• pp.1-7
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• 2004

We performed two-dimensional (20) computer-based modeling and simulation of FinFET by solving the coupled Poisson-Schrodinger equations quantum-mechanically in a self-consistent manner. The simulation results are carefully investigated for FinFET with gate length(Lg) varying from 10 to 80nm and with a Si-fin thickness($T_{fin}$) varying from 10 to 40nm. Current-voltage (I-V) characteristics are compared with the experimental data. Device optimization has been performed in order to suppress the short-channel effects (SCEs) including the sub-threshold swing, threshold voltage roll-off, drain induced barrier lowering (DIBL). The quantum-mechanical simulation is compared with the classical appmach in order to understand the influence of the electron confinement effect. Simulation results indicated that the FinFET is a promising structure to suppress the SCEs and the quantum-mechanical simulation is essential for applying nano-scale device structure.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.29A no.4
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• pp.33-37
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• 1992

AlGaAs/GaAs quantum well delta-doped channel FET's have been successfully fabricated using by low-pressure metalorganic chemical vapor deposition(LP-MOCVD). The FET's with a gate dimension of 1.8$\mu$m $\times$ 100$\mu$m have a maximum transconductance of 190 mS/mm and a maximum current density of 425 mA/nm. The devices show extremely broad transconductances with a large voltage swing of 2.4V. The S-parameter measurements have indicated that the current gain and power gain cutoff frequencies of the device were 7 and 15 GHz, respectively. These values are among the best performance reported for GaAs based heterojunction FET's with a similar device geometry.

• Transactions on Electrical and Electronic Materials
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• v.8 no.3
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• pp.139-142
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• 2007

Organic field-effect transistor (FET) based on a copper Phthalocyanine (CuPc) material as an active layer and a $SiO_2$ as a gate insulator were fabricated and analyzed. We measured the typical FET characteristics of CuPc in air. The electrical characteristics of the CuPc FET device were analyzed by a Maxwell-Wagner model. The Maxwell-Wagner model employed in analyzing double-layer dielectric system was helpful to explain the C-V and I-V characteristics of the FET device. In order to further clarity the channel formation of the CuPc FET, optical second harmonic generation (SHG) measurement was also employed. Interestingly, SHG modulation was not observed for the CuPc FET. This result indicates that the accumulation of charge from bulk CuPc makes a significant contribution.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.561-561
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• 2012

Graphene, two dimensional single layer of carbon atoms, has tremendous attention due to its superior property such as fast electron mobility, high thermal conductivity and optical transparency, and also found many applications such as field-effect transistors (FET), energy storage and conversion, optoelectronic device, electromechanical resonators and chemical sensors. Several techniques have been developed to form the graphene. Especially chemical vapor deposition (CVD) is a promising process for the large area graphene. For the electrically isolated devices, the graphene should be transfer to insulated substrate from Cu or Ni. However, transferred graphene has serious drawback due to remaining polymeric residue during transfer process which induces the poor device characteristics by impurity scattering and it interrupts the surface functionalization for the sensor application. In this study, we demonstrate the characteristics of solution-gated FET depending on the removal of polymeric residues. The solution-gated FET is operated by the modulation of the channel conductance by applying a gate potential from a reference electrode via the electrolyte, and it can be used as a chemical sensor. The removal process was achieved by several solvents during the transfer of CVD graphene from a copper foil to a substrate and additional annealing process with H2/Ar environments was carried out. We compare the properties of graphene by Raman spectroscopy, atomic force microscopy(AFM), and X-ray Photoelectron Spectroscopy (XPS) measurements. Effects of residual polymeric materials on the device performance of graphene FET will be discussed in detail.