• Journal of Power Electronics
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• 제16권1호
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• pp.351-361
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• 2016

Power quality is a critical issue in distribution systems, where a dynamic voltage restorer (DVR) is commonly used to mitigate the voltage disturbances for loads. This paper deals with a nonlinear control for the three-phase four-wire (3P-4W) DVR under a grid voltage unbalance and nonlinear loads in the distribution system, where a novel control scheme based on the feedback linearization technique is proposed. Through feedback linearization, a nonlinear model of a DVR with a PWM voltage-source inverter (VSI) and LC filters is linearized. Then, the controller design of the linearized model is performed by applying the linear control theory, where the load voltages are kept constant by controlling the d-q-0 axis components of the DVR output voltages. To keep the load voltage unchanged, an in-phase compensation strategy is employed, where the load voltages are recovered to be the same as the previous voltage without a change in the magnitude. With this strategy, the performance of the DVR becomes faster and more stable even under unbalanced source voltages and nonlinear loads. The validity of the proposed control strategy has been verified by simulation and experimental results.

• Journal of Power Electronics
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• 제14권4호
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• pp.704-711
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• 2014

This paper proposes a combined fuzzy adaptive sliding-mode voltage controller (FASVC) for a three-phase UPS inverter. The proposed FASVC encapsulates two control terms: a fuzzy adaptive compensation control term, which solves the problem of parameter uncertainties, and a sliding-mode feedback control term, which stabilizes the error dynamics of the system. To extract precise load current information, the proposed method uses a conventional load current observer instead of current sensors. In addition, the stability of the proposed control scheme is fully guaranteed by using the Lyapunov stability theory. It is shown that the proposed FASVC can attain excellent voltage regulation features such as a fast dynamic response, low total harmonic distortion (THD), and a small steady-state error under sudden load disturbances, nonlinear loads, and unbalanced loads in the existence of the parameter uncertainties. Finally, experimental results are obtained from a prototype 1 kVA three-phase UPS inverter system via a TMS320F28335 DSP. A comparison of these results with those obtained from a conventional sliding-mode controller (SMC) confirms the superior transient and steady-state performances of the proposed control technique.

• Journal of Power Electronics
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• 제15권2호
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• pp.504-517
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• 2015

This paper presents a novel switching voltage model and an offset-based pulse width modulation (PWM) scheme for multilevel inverters with unbalanced DC sources. The switching voltage model under a DC voltage imbalance will be formulated in general form for multilevel neutral-point-clamped topologies. Analysis of the reference switching voltages from active and non-active switching voltage components in abc coordinates can enable voltage implementation for an unbalanced DC-source condition. Offset voltage is introduced as an indispensable variable in the switching voltage model for multilevel voltage-source inverters. The PWM performance is controlled through the design of two offset components in a subsequence. One main offset may refer to the common mode voltage, and the other offset restricts its effect on the quality of PWM control in related DC levels. The PWM quality can be improved as the switching loss is reduced in a discontinuous PWM mode by setting the local offset, which is related to the load currents. The validity of the proposed algorithm is verified by experimental results.

• 한국정보처리학회논문지
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• 제4권11호
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• pp.2923-2930
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• 1997

본 논문에서는 최근에 관심을 모으고 있는Table Look- Up형의 FPGA를 위한 다출력 함수로직 합성 알고리즘에 대해 기술한다. 본 고에서 제안하는 TLU형 FPGA를 위한 다출력 함수 로직 합성 방법은 기능적 분해 방법을 사용하였으며, 이 방법을 이용한 2가지의 새로운 알고리즘을 설명한다. 첫번째는 한 출력에 적용한 Rofh-Karp 알고리즘을 다출력에 웅용할 수 있도록 확장하였으며, 두 번째는 분해과정에서 공통 분해 함수를 찾는 효과적 인 알고리즘을 제안한다. 기술 매핑의 최적화 대상은 CLB 개수를 고려했으며, 벤치마크 테스트를 통한 일반적인 회로에 적용성 검증, 기존 알고리즘과의 성능 비교 및 개선에 대해 연구하였다. 논리 설계 합성기 구성 과정에서 새로운 알고리즘을 구현하여 실험한 결과를 기존의 다출력 함수 분해 방법과 비교하면 CLB 의 개수, 네트 수 등 성능과 수행 시간에서 매우 만족할 만한 결과를 얻었다．

• Journal of Power Electronics
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• 제17권3호
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• pp.704-715
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• 2017

For three-phase synchronization applications, the synchronous reference frame phase-locked loop (SRF-PLL) is probably the most widely used technique due to its ease of implementation and satisfactory phase tracking performance under ideal grid conditions. However, under unbalanced and distorted grid conditions, its performance tends to worsen. To deal with this problem, a variety of filtering stages have been proposed and used in SRF-PLLs for the rejection of disturbance components at the cost of degrading the dynamic performance. In this paper, to improve dynamic performance without compromising the filtering capability, an effective hybrid filtering stage is proposed and incorporated into the inner loop of a quasi-type-1 PLL (QT1-PLL). The proposed filtering stage is a combination of a moving average filter (MAF) and a modified delay signal cancellation (DSC) operator in cascade. The time delay caused by the proposed filtering stage is smaller than that in the conventional MAF-based and DSC-based PLLs. A small-signal model of the proposed PLL is derived. The stability is analyzed and parameters design guidelines are given. The effectiveness of the proposed PLL is confirmed through experimental results.

• 전기학회논문지
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• 제64권10호
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• pp.1460-1468
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• 2015

As the number of IoT service increases, the interest of lightweight block cipher algorithm, which consists of simple operations with low-power and high speed, is growing. LEA(Leightweight Encryption Algorithm) is recently adopted as one of lightweight encryption standards in Korea. In this paper a pipeline LEA architecture is proposed to process large amounts of data with high throughput. The proposed pipeline LEA can communicate with external modules in the 32-bit I/O interface. It consists of input, output and encryption pipeline stages which take 4 cycles using a muti-cycle pipeline technique. The experimental results showed that the proposed pipeline LEA achieved more than 7.5 Gbps even though the key length was varied. Compared with the previous high speed LEA in accordance with key length of 128, 192, and 256 bits, the throughput of the pipeline LEA was improved 6.45, 7.52, and 8.6 times. Also the throughput per area was improved 2, 1.82, and 2.1 times better than the previous one.

• 동력기계공학회지
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• 제15권5호
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• pp.91-96
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• 2011

The handling ability of containers at the terminal strongly depends on the performance of the cargo handling system such as RTGC(Rubber Tired Gantry Crane) and RMGC(Rail Mounted Gantry Crane). This paper introduces a guide line measurement system on the operating condition, in which two camera are installed to detect the guide line. Because the line tracking is the basic technique for control system design of RTGC, it is necessary to develop a useful and reliable measurement system. If the displacement and angle of the RTGC relative to a guide line as the trajectory to follow is obtained, the position of RTGC is automatically calculated. Therefore, in this paper, a camera-based measurement system is introduced. The proposed measurement system is robust against light fluctuation and cracks of the guide line. This system consists of two camera and a PC which are installed at the lower side of the RTGC. Two edges of the guide line are detected from an input image taken by the cameras in the moving state, and these positions are determined in a Hough parameter space by using the Hough transformation method. From the experimental results, the accuracy and usefulness of the proposed system is evaluated by comparing other instruments.

• 한국소음진동공학회:학술대회논문집
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• 한국소음진동공학회 2004년도 추계학술대회논문집
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• pp.349-353
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• 2004

A study on optimal placement of constrained layer damping treatment for vibration control of automotive panels is presented. The effectiveness of damping treatment depends upon design parameters such as choice of damping materials, locations and size of the treatment. This paper proposes a CAE (Computer Aided Engineering) methodology based on finite element analysis to optimize damping treatment. From the equivalent modeling technique, it is found that the best damping performance occurs as the viscoelstic patch is placed by means of the modal strain energy method of bare structural panels to identify flexible regions, which in turn facilitates optimizations of damping treatment with respect to location and size. Different configurations of partially applied damping layer treatment have been analyzed for their effectiveness in realizing maximum system damping with minimum mass of the applied damping material. Moreover, simulated frequency response function of the automotive roof with and without damping treatments are compared, which show the benefits of applying damping treatment. Finally, the optimized damping treatment configuration is validated by comparing the locations and the size of the treatment with that of an experimental modal test conducted on roof compartment.

• 한국멀티미디어학회논문지
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• 제19권8호
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• pp.1310-1319
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• 2016

Face detection is the first step in a wide range of face applications. However, detecting faces in the wild is still a challenging task due to the wide range of variations in pose, scale, and occlusions. Recently, many deep learning methods have been proposed for face detection. However, further improvements are required in the wild. Another important issue to be considered in the face detection is the computational complexity. Current state-of-the-art deep learning methods require a large number of patches to deal with varying scales and the arbitrary image sizes, which result in an increased computational complexity. To reduce the complexity while achieving better detection accuracy, we propose a fully convolutional network-based face detection that can take arbitrarily-sized input and produce feature maps (heat maps) corresponding to the input image size. To deal with the various face scales, a multi-scale network architecture that utilizes the facial components when learning the feature maps is proposed. On top of it, we design multi-task learning technique to improve detection performance. Extensive experiments have been conducted on the FDDB dataset. The experimental results show that the proposed method outperforms state-of-the-art methods with the accuracy of 82.33% at 517 false alarms, while improving computational efficiency significantly.

• Journal of Power Electronics
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• 제17권6호
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• pp.1391-1401
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• 2017

In this paper, a secondary resonance half-bridge dc-dc converter with an inductive output filter is presented. The primary side of such a converter utilizes asymmetric pulse width modulation (APWM) to achieve zero-voltage switching (ZVS) of the switches, and clamps the voltage of the switch to the input voltage. In addition, zero current switching (ZCS) of the output diode is achieved by a half-wave rectifier circuit with a filter inductor and a resonant branch in the secondary side of the proposed converter. Thus, the switching losses and diode reverse-recovery losses are eliminated, and the performance of the converter can be improved. Furthermore, an inductive output filter exists in the converter reduce the output current ripple. The operational principle, performance analysis and design equation of this converter are given in this paper. The analysis results show that the output diode voltage stress is independent of the duty cycle, and that the voltage gain is almost linear, similar to that of the isolation Buck-type converter. Finally, a 200V~380V input, 24V/2A output experimental prototype is built to verify the theoretical analysis.