• Journal of the Korea Society of Computer and Information
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• v.23 no.11
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• pp.103-109
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• 2018

This paper presents an idea and framework to automate a full cycle business process management and re-engineering by integrating traditional business process management systems, process mining, data mining, machine learning, and simulation. We build our framework on the cloud-based platform such that various data sources can be incorporated. We design our systems to be extensible so that not only beneficial for practitioners of BPM, but also for researchers. Our framework can be used as a test bed for researchers without the complication of system integration. The automation of redesigning phase and selecting a baseline process model for deployment are the two main contributions of this study. In the redesigning phase, we deal with both the analysis of the existing process model and what-if analysis on how to improve the process at the same time, Additionally, improving a business process can be applied in a case by case basis that needs a lot of trial and error and huge data. In selecting the baseline process model, we need to compare many probable routes of business execution and calculate the most efficient one in respect to production cost and execution time. We also discuss the challenges and limitation of the framework, including the systems adoptability, technical difficulties and human factors.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.33 no.5
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• pp.775-785
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• 2023

As processor technology advances, it has accelerated ISA extensions and increased the complexity of micro-architectures, leading to a continued rise in the importance of processor validation techniques. Recently, various fuzzing techniques have been introduced to discover undocumented instructions, and this study highlights the shortcomings of existing undocumented instruction fuzzing techniques and presents our observation on error cases in the latest processors from Intel and AMD. In particular, we analyzes the causes of false positives resulting from the fuzzer incorrectly judging CPU instruction length and proposes the length determination technique based on instruction execution information to improve accuracy.

• Journal of the Korea Society of Computer and Information
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• v.26 no.9
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• pp.1-12
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• 2021

In this paper, we propose a tool called ARCAV (Atomatic Recovery of CUDA Atomicity violation) to automatically repair atomicity violations in GPU (Graphics Processing Unit) program. ARCAV monitors information of every barrier and memory to make actual memory writes occur at the end of the barrier region or to make the program execute barrier region again. Existing methods do not repair atomicity violations but only detect the atomicity violations in GPU programs because GPU programs generally do not support lock and sleep instructions which are necessary for repairing the atomicity violations. Proposed ARCAV is designed for GPU execution model. ARCAV detects and repairs four patterns of atomicity violations which represent real-world cases. Moreover, ARCAV is independent of memory hierarchy and thread configuration. Our experiments show that the performance of ARCAV is stable regardless of the number of threads or blocks. The overhead of ARCAV is evaluated using four real-world kernels, and its slowdown is 2.1x, in average, of native execution time.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.9
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• pp.1825-1838
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• 2012

This paper proposes a fast face detection and tracking method which uses depth images as well as RGB images. It consists of the face detection procedure and the face tracking procedure. The face detection method basically uses an existing method, Adaboost, but it reduces the size of the search area by using the depth information and skin color. The proposed face tracking method uses a template matching technique and incorporates an early-termination scheme to reduce the execution time further. The results from implementing and experimenting the proposed methods showed that the proposed face detection method takes only about 39% of the execution time of the existing method. The proposed tracking method takes only 2.48ms per frame. For the exactness, the proposed detection method and previous method showed a same detection ratio but in the error ratio, which is about 0.66%, the proposed method showed considerably improved performance. In all the cases except a special one, the tracking error ratio is as low as about 1%. Therefore, we expect the proposed face detection and tracking methods can be used individually or in combined for many applications that need fast execution and exact detection or tracking.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.10 no.5
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• pp.209-217
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• 1985

Using the Reed-Muller Codes, the encoder and decoder system has been designed and tested in this paper. The error correcting capability of this code is [J/2} or less and the error correcting procedure can be implemented easily by using simple logic circuitry. The encoding and decoding circuits are obtained by the cyclic property and for the O15, 11) Reed-Muller code majority-logic decoding is taken. The performance is measured in error probability and weight destribution. The encoder and decoder system has been designed, implemented and interfaced with the microcomputer by using the 8255 chip. Experimental results show that the system has single error-correcting capability and total execution time for a data is about 70usec. When the probability of channel error is $10^{-6}$~$10^{-4}$ the system using the (15, 11) Reed-Muller code works very good.

• The KIPS Transactions:PartC
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• v.14C no.2
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• pp.163-170
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• 2007

The next generation communication environment consists of various wireless access networks with distinct features that are configured as an overlay topology. In the network environments, the frequency of hand overs should be minimized and the error propagation should be solved in order to provide high-quality multimedia services to mobile users. Therefore, we propose an performance enhancement approach, based on mSCTP, that provides high quality multimedia services to mobile users by ameliorating the error propagation problem. We utilizes the following four functions: 1) the separation of transmission paths according to the types of frames. 2) retransmission strategy to minimize the loss rate of frames, 3) Foced vertical handover execution by utilizing bicasting, 4) using the stability period in order to reduce the effect of the ping pong phenomenon. The simulation results show that the proposed approach provides seamless multimedia service to mobile users by achieving error resilience.

• Progress in Medical Physics
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• v.30 no.4
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• pp.128-138
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• 2019

Purpose: Segmental analysis of volumetric modulated arc therapy (VMAT) is not clinically used for compositional error source evaluation. Instead, dose verification is routinely used for plan-specific quality assurance (QA). While this approach identifies the resultant error, it does not specify which machine parameter was responsible for the error. In this research study, we adopted an approach for the segmental analysis of VMAT as a part of machine QA of linear accelerator (LINAC). Methods: Two portal dose QA plans were generated for VMAT QA: a) for full arc and b) for the arc, which was segmented in 12 subsegments. We investigated the multileaf collimator (MLC) position and dosimetric accuracy in the full and segmented arc delivery schemes. A MATLAB program was used to calculate the MLC position error from the data in the dynalog file. The Gamma passing rate (GPR) and the measured to planned dose difference (DD) in each pixel of the electronic portal imaging device was the measurement for dosimetric accuracy. The eclipse treatment planning system and a MATLAB program were used to calculate the dosimetric accuracy. Results: The maximum root-mean-square error of the MLC positions were <1 mm. The GPR was within the range of 98%-99.7% and was similar in both types of VMAT delivery. In general, the DD was <5 calibration units in both full arcs. A similar DD distribution was found for continuous arc and segmented arcs sums. Exceedingly high DD were not observed in any of the arc segment delivery schemes. The LINAC performance was acceptable regarding the execution of the VMAT QA plan. Conclusions: The segmental analysis proposed in this study is expected to be useful for the prediction of the delivery of the VMAT in relation to the gantry angle. We thus recommend the use of segmental analysis of VMAT as part of the regular QA.

• The KIPS Transactions:PartA
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• v.18A no.2
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• pp.61-68
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• 2011

Memory error debugging is one of the most critical processes in improving software quality. However, due to the extensive time consumed to debug, the enhancement often leads to a huge bottle neck in the development process of mobile devices. Most of the existing memory error detection tools are based on static error detection; however, the tools cannot be used in mobile devices due to their use of large working memory. Therefore, it is challenging for mobile device vendors to deliver high quality mobile devices to the market in time. In this paper, we introduce "PinMemcheck", a pin-based memory error detection tool, which detects all potential memory errors within $1.5{\times}$ execution time overhead compared with that of a baseline configuration by applying the Pin's binary instrumentation process and a simple data structure.

• Journal of the Korea Society of Computer and Information
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• v.17 no.5
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• pp.59-70
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• 2012

RSA-CRT is one of the commonly used techniques to speedup RSA operation. Since RSA-CRT performs its operations based on the modulus of two private primes, it is about four times faster than RSA. In RSA, the two primes are normally thrown away after generating the public key pair. However, in RSA-CRT, the two primes are directly used in RSA operations. This led to hardware fault attacks which can be used to factor the public modulus. The most common way to counter these attacks is based on error propagation. In these schemes, all the outputs of RSA are affected by the infected error which makes it difficult for an adversary to use the output to factor the public modulus. However, the error propagation has sequentialized the RSA operation. Moreover, these schemes have been found to be still vulnerable to hardware fault attacks. In this paper, we propose two new RSA-CRT schemes which are both resistant to hardware fault attack and support parallel execution: one uses common modulus and the other one perform operations in each prime modulus. Both proposed schemes takes about a time equal to two exponentiations to complete the RSA operation if parallel execution is fully used and can protect the two private primes from hardware fault attacks.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.45 no.10
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• pp.863-871
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• 2017

LMS (least mean square) algorithm widely used in the AVCS (active vibration control system) of helicopters calculates control input using the forward path transfer function and error signal. If the error signal is sinusoidal, it can be represented as the combination of cosine and sine functions with frequency and phase synchronized with the reference signal. The control input also has the same frequency, therefore control algorithm can be simply implemented if the cosine and the sine amplitudes of the control input are calculated and the frequency and phase of the reference signal are used. Calculation of the control input is implemented as simple matrix operation and the change of the control command is slower than the frequency of the error signal, consequently control algorithm can be operated at lower frequency. The signal processing algorithm extracting cosine and sine components of the error signals are modeled using Simulink and PIL (processor-in-the-loop) mode simulation was executed for real-time performance evaluation.