• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.11
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• pp.1686-1690
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• 1989

Using the anisotropic etching characteristics of N2H4-H2O solutions, Si diaphragm was fabricated for the integrated sensors. The optimal composition and temperature of the etching solution in (100) Si etching process was established to be 50mol% N2H4 in H2O at 105\ulcorner\ulcorner for both higher etch rate (=2.6\ulcorner/min) and better surface quality of etched (100) planes. Based on the above optimal etching condition, the electrochemical etch-stop technique was employed to form n-type Si diaphragm having a thickness of 20\ulcorner and the thickness of diapragm could exactly be controlled to 20\ulcorner\ulcorner.

• Proceedings of the KIEE Conference
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• 1989.07a
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• pp.295-298
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• 1989

Using the anisotropic etching characteristics or $N_2H_4-H_2O$ solution, Si diaphragm was fabricated for the integrated sensor. The optimal composition and temperature of the solution in Si etching process was established to be 50mol% $N_2H_4$ in water at $105{\pm}2^{\circ}C$ for both higher etch rate(=$2.6{\mu}m/min$) and better surface quality of etched {100} planes. Under the optimal etching condition, the electrochemical etch stop technique was employed to form Si diaphragm for pressure sensor and diaphragm thickness was exactly controlled to $20{\pm}2{\mu}m$.

• Journal of the Institute of Convergence Signal Processing
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• v.9 no.2
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• pp.146-153
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• 2008

Integrated humidity sensor system with two stages operational amplifier has been designed and fabricated by $0.8{\mu}m$ analog mixed CMOS technology. The system (28 pin and $2mm{\times}4mm$) consisted of Wheatstone-bridge type humidity sensor, resistive type humidity sensor, temperature sensors and operational amplifier for signal amplification and process in one chip. The poly-nitride etch stop process has been tried to form the sensing area as well as trench in a standard CMOS process. This modified technique did not affect the CMOS devices in their essential characteristics and gave an allowance to fabricate the system on same chip by standard process. The operational amplifier showed the stable operation so that unity gain bandwidth was more than 5.46 MHz and slew rate was more than 10 V/uS, respectively. The drain current of n-channel humidity sensitive field effect transistor (HUSFET) increased from 0.54 mA to 0.68 mA as the relative humidity increased from 10 to 70 %RH.

• Journal of Sensor Science and Technology
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• v.1 no.2
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• pp.131-145
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• 1992

This paper has been described a process technology for the fabrication of Si-on-insulator(SOI) transducers and circuits. The technology utilizes Si-wafer direct bonding(SDB) and mechanical-chemical(M-C) local polishing to create a SOI structure with a high-qualify, uniformly thin layer of single-crystal Si. The electrical and piezoresistive properties of the resultant thin SOI films have been investigated by SOI MOSFET's and cantilever beams, and confirmed comparable to those of bulk Si. Two kinds of pressure transducers using a SOI structure have been proposed. The shifts in sensitivity and offset voltage of the implemented pressure transducers using interfacial $SiO_{2}$ films as the dielectrical isolation layer of piezoresistors were less than -0.2% and +0.15%, respectively, in the temperature range from $-20^{\circ}C$ to $+350^{\circ}C$. In the case of pressure transducers using interfacial $SiO_{2}$ films as an etch-stop layer during the fabrication of thin Si membranes, the pressure sensitivity variation can be controlled to within a standard deviation of ${\pm}2.3%$ from wafer to wafer. From these results, the developed SDB process and the resultant SOI films will offer significant advantages in the fabrication of integrated microtransducers and circuits.

• Journal of IKEEE
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• v.1 no.1 s.1
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• pp.1-10
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• 1997

It is well-known that rectangular bulk-Si sensors prepared by etch or epi etch-stop micromachining technology are already in practical use today, but the conventional bulk-Si sensor shows some drawbacks such as large chip size and limited applications as silicon sensor device is to be miniaturized. We consider a circular-shape SOI(Silicon-On-Insulator) micro-cavity technology to facilitate multiple sensors on very small chip, to make device easier to package than conventional sensor like pressure sensor and to provide very high over-pressure capability. This paper demonstrates the cross-functional results for stress analyses(targeting $5{\mu}m$ deflection and 100MPa stress as maximum at various applicable pressure ranges), for finding permissible diaphragm dimension by output sensitivity, and piezoresistive sensor theory from two-type SOI structures where the double SOI structure shows the most feasible deflection and small stress at various ambient pressures. Those results can be compared with the ones of circular-shape bulk-Si based sensor$^{[17]}. The SOI micro-cavity formed the sensors is promising to integrate with calibration, gain stage and controller unit plus high current/high voltage CMOS drivers onto monolithic chip.

• Proceedings of the KIEE Conference
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• 1996.11a
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• pp.425-427
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• 1996

New fabrication technique was developed to make three dimensional silicon microstructure with five fold vertical steps through entire wafer thickness. Each step is pre-defined on multiply stacked thermal oxide and silicon nitride (O/N) layers by photolithographies. Multi-stepped silicon microstructure is formed by anisotropic etch in aqueous KOH solution with the patterned nitride film as masking layer. Fabricated microstructure consists of four $16{\mu}m$ thick flexural spring beams, $290{\mu}m$ thick proof mass, mesas for overrange stop with $10{\mu}m$ height from the surface of the proof mass, and the other mesas and V grooves used for assembling this structure to the packaging frame of pendulous servo accelerometer. Using the numerical finite element method (FEM) simulator: ABAQUS, mechanical characteristics of the fabricated microstructure by the developed technique was compared with those of the same structure processed by one step silicon bulk etch followed by oxidation and patterning the etched region.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.287-287
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• 2011

ITRS(international technology roadmap for semiconductors)에 따르면 MOS (metal-oxide-semiconductor)의 CD(critical dimension)가 45 nm node이하로 줄어들면서 poly-Si/SiO2를 대체할 수 있는 poly-Si/metal gate/high-k dielectric이 대두되고 있다. 일반적으로 metal gate를 식각시 정확한 CD를 형성시키기 위해서 plasma를 이용한 RIE(reactive ion etching)를 사용하고 있지만 PIDs(plasma induced damages)의 하나인 PICD(plasma induced charging damage)의 발생이 문제가 되고 있다. PICD의 원인으로 plasma의 non-uniform으로 locally imbalanced한 ion과 electron이 PICC(plasma induced charging current)를 gate oxide에 발생시켜 gate oxide의 interface에 trap을 형성시키므로 그 결과 소자 특성 저하가 보고되고 있다. 그러므로 본 연구에서는 이에 차세대 MOS의 metal gate의 식각공정에 HDP(high density plasma)의 ICP(inductively coupled plasma) source를 이용한 중성빔 시스템을 사용하여 PICD를 줄일 수 있는 새로운 식각 공정에 대한 연구를 하였다. 식각공정조건으로 gas는 HBr 12 sccm (80%)와 Cl2 3 sccm (20%)와 power는 300 w를 사용하였고 200 eV의 에너지로 식각공정시 TEM(transmission electron microscopy)으로 TiN의 anisotropic한 형상을 볼 수 있었고 100 eV 이하의 에너지로 식각공정시 하부층인 HfO2와 높은 etch selectivity로 etch stop을 시킬 수 있었다. 실제 공정을 MOS의 metal gate에 적용시켜 metal gate/high-k dielectric CMOSFETs의 NCSU(North Carolina State University) CVC model로 effective electric field electron mobility를 구한 결과 electorn mobility의 증가를 볼 수 있었고 또한 mos parameter인 transconductance (Gm)의 증가를 볼 수 있었다. 그 원인으로 CP(Charge pumping) 1MHz로 gate oxide의 inteface의 분석 결과 이러한 결과가 gate oxide의 interface trap양의 감소로 개선으로 기인함을 확인할 수 있었다.

• Journal of Electrical Engineering and Technology
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• v.6 no.1
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• pp.119-122
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• 2011

A new high speed AFM probe has been proposed and fabricated. The probe is integrated with PZT actuated cantilever realized in bulk silicon wafer using heavily boron doped silicon as an etch stop layer. The cantilever thickness can be accurately controlled by the boron diffusion process. Thick SCS cantilever and integrated PZT actuator make it possible to be operated at high speed for fast imaging. The resonant frequency of the fabricated probe is 92.9 kHz and the maximum deflection is 5.3 ${\mu}m$ at 3 V. The fabricated probe successfully measured the surface of standard sample in an AFM system at the scan speed of 600${\mu}m$/sec.

• 제어로봇시스템학회:학술대회논문집
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• 1996.10b
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• pp.415-418
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• 1996

Etching Process, one of the most important process in semiconductor fabrication, has input control part of which components are pressure, gas flow, RF power and etc., and plasma gas which is complex and not exactly understood is used to etch wafer in etching chamber. So this process has not real-time feedback controller based on input-output relation, then it uses EPD(End Point Detection) signal to determine when to start or when to stop etching. Various type EPD controller control etching process using EPD signal obtained from optical intensity of etching chamber. In development EPD controller we concentrate on compensation of this signal intensity and setting the relative signal magnitude at first of etching. We compensate signal intensity using neural network learning method and set the relative signal magnitude using fuzzy inference method. Potential of this method which improves EPD system capability is proved by experiences.

• Proceedings of the KIEE Conference
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• 1993.11a
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• pp.207-209
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• 1993

In this paper, an electrostatic silicon micro actuator has been designed and fabricated using the micro machining technology. The actuator consists of two counter electrodes. One is an Al film deposited on a pyrex glass, and the other is a circular corrugated diaphragm with boron doped. The diaphragm is fabricated by boron etch stop technique using an anisotropic etchant, EPW.