• Laser Solutions
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• v.17 no.4
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• pp.20-23
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• 2014

In printed electronics, printing rolls are used to transfer electronic ink onto a flexible substrate. Generally printing rolls are patterned in microscale by the indirect laser method. Since based on the wet etch process, the indirect method is neither environment-friendly nor suitable for making a printing roll with patterns narrower than $20{\mu}m$. In this paper, we have directly engraved micro-patterns into a Zn-coated metal specimens using a picosecond laser in order both to engrave $10{\mu}m$-wide patterns and to improve the pattern profile. Experiments showed that it is possible to engrave $10{\mu}m$-wide patterns with an a rectangular-shaped profile which is necessary for the dimensionally accurate printing.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.13 no.3
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• pp.183-187
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• 2000

In this study the SrBi$_2$Ta$_2$$O_{9}$ (SBT) thin films were etched by using magnetically enhanced inductively coupled Ar/CHF$_3$plasma as function of CHF$_3$/(Ar+CHF$_3$)gas mixing ratio. Maximum etch rate of SBT thin films was 1650 $\AA$/min and the selectivities of SBT to Pt and photoresist(PR) were 1.35 and 0.94 respectively under CHF$_3$/(Ar+CHF$_3$) of 0.1 For study on etching mechanism of SBT thin film X-ray photoelectron spectroscopy (XPS) surface analyses and secondary ion mass spectrometry (SIMS) mass analysis of etched SBT surfaces were performed. Among the elements of SBT thin film. M(Sr, Bi, Ta)-O bonds are broken by Ar ion bombardment and form SrF and TaF$_2$by chemical reaction with F. SrF and TaF$_2$are removed more easily by Ar ion bombardment. Scanning electron microscopy(SEM) was used for the profile examination of etched SBT film and the cross-sectional SEM profile of etched SBT film under CHF$_3$(Ar+CHF$_3$) of 0.1 was about 85$^{\circ}$X>.

• Korean Journal of Metals and Materials
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• v.48 no.11
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• pp.1028-1034
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• 2010

In the development of 3D package, through silicon via (TSV) formation technology by using deep reactive ion etching (DRIE) is one of the key processes. We performed the Bosch process, which consists of sequentially alternating the etch and passivation steps using $SF_6$ with $O_2$ and $C_4F_8$ plasma, respectively. We investigated the effect of changing variables on vias: the gas flow time, the ratio of $O_2$ gas, source and bias power, and process time. Each parameter plays a critical role in obtaining a specified via profile. Analysis of via profiles shows that the gas flow time is the most critical process parameter. A high source power accelerated more etchant species fluorine ions toward the silicon wafer and improved their directionality. With $O_2$ gas addition, there is an optimized condition to form the desired vertical interconnection. Overall, the etching rate decreased when the process time was longer.

• Proceedings of the KIEE Conference
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• 1998.07d
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• pp.1294-1296
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• 1998

Platinum thin films which hardly form volatile compounds with any reactive gas at normal process temperature was etched in Inductively Coupled Plasma (ICP) using Ar/HBr/$Cl_2$ gases. It is observed that the etch rate of platinum is reduced as increasing of HBr/$Cl_2$ gas mixing ratio when Ar gas ratio is fixed. However, we obtain good etching profile of platinum films without unwanted residues in 90% Ar/5% HBr/5% $Cl_2$ gas mixing ratio.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2006.05a
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• pp.659-660
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• 2006

High-aspect-ratio(max. 12.5) microchannels with excellent surface quality and good shape uniformity have been realized utilizing laser-induced etching technique. Etch width and depth variations depend largely upon process variables such as laser power and etchant concentration. Etchant concentration in association with viscosity also influence on the cross-sectional profile of the channels. The optimum process conditions for the fabrication of high-aspect-ratio microchannels applicable to micro thermal devices are demonstrated.

• 한국정보디스플레이학회:학술대회논문집
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• 2000.01a
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• pp.77-78
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• 2000

We verified the charged static electricity on LCD glass influences upon the etching uniformity of dry etching process by plasma. In the TFT-LCD manufacturing process, we mainly paid attention to eliminate the static electricity for TFT reliability. The static electricity caused the serious ununiformity of etching surface profile and etching rate in the dry etch process. Through our experiment on the made static electricity from -200V to -1000V, it was confirmed that the static electricity on LCD glass caused the etching rate variation of $1.5%{\sim}15%$. We recommend the etching process equipment for LCD manufacturing have to establish the soft X-ray exposure module system for eliminating the static electricity inside the loading and unloading chamber.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.25 no.3
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• pp.236-240
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• 2012

Limiting thermal exposure time using rapid thermal processing(RTP) has emerged as promising simplified process for manufacturing of solar cell in a continuous way. This paper reports the simplification of co-firing using RTP. Actual temperature profile for co-firing after screen printing is a key issue for high-quality metal-semiconductor contact. The plateau time during the firing process were varied at $450^{\circ}C$ for 10~16 sec. Glass frit in Ag paste etch anti-reflection layer with plateau time. Glass frit in Ag paste is important for the Ag/Si contact formation and performances of crystalline Si solar cell. We achieved 17.14% efficiency with optimum conditions.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.08a
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• pp.277-277
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• 2011

디스플레이의 기술발전에 의해 대면적 고해상도의 LCD가 제작되어 왔다. 이에 따라 LCD 점등검사를 위한 Probe Unit의 기술 또한 급속도로 발전하고 있다. 고해상도에 따라 TFT LCD pad가 미세피치화 되어가고 있으며, panel의 검사를 위한 Probe 또한 30 um 이하의 초미세피치를 요구하고 있다. 따라서, 초미세 pitch의 LCD panel의 점등검사를 위한 Probe Unit의 개발이 시급하가. 본 연구에서는 30 um 이하의 미세피치의 Probe block을 위한 Slit wafer의 식각 공정 조건을 연구하였다. Si 공정에서 식각율과 식각깊이에 따른 profile angle의 목표를 설정하고, 식각조건에 따라 이 두 값의 변화를 관측하였다. 식각실험으로 Si DRIE 장비를 이용하여, chamber 압력, cycle time, gas flow, Oxygen의 조건에 따라 각각의 단면 및 표면을 SEM 관측을 통해 최적의 식각 조건을 찾고자 하였다. 식각율은 5um/min 이상, profile angle은 $90{\pm}1^{\circ}$의 값을 목표로 하였다. 이 때 최적의 식각조건은 Etching : SF6 400 sccm, 10.4 sec, passivation : C4F8 400 sccm, 4 sec의 조건이었으며, 식각공정의 Coil power는 2,600 W이었다. 이러한 조건의 공정으로 6 inch Si wafer에 공정한 결과 균일한 식각율 및 profile angle 값을 보였으며, oxygen gas를 미량 유입함으로써 식각율이 균일해짐을 알 수 있었다. 결론적으로 최적의 Slit wafer 식각 조건을 확립함으로써 Probe Unit을 위한 Pin 삽입공정 또한 수율 향상이 기대된다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.05b
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• pp.67-70
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• 2001

$SrBi_2Ta_2O_9$ thin films were etched at high-density $Cl_2/CF_4/Ar$ in inductively coupled plasma system. The chemical reactions on the etched surface were studied with x-ray photoelectron spectroscopy and secondary ion mass spectrometry. The etching of SBT thin films in $Cl_2/CF_4/Ar$ were chemically assisted reactive ion etching. The maximum etch rate was 1060 Am /min in $Cl_2$(20)/CF_4(20)/Ar(80). The small addition of $Cl_2$ into $CF_4$(20)/Ar(80) plasma will decrease the fluorine radicals and the increase CI radical. The etch profile of SBT thin films in $Cl_2/CF_4/Ar$ plasma is steeper than in $CF_4$/Ar plasma.Ā저會Ā저ﶖ⨀⡌ឫഀĀ᐀會Ā᐀㡆ﶖ⨀쁌ឫഀĀ᐀會Ā᐀遆ﶖ⨀郞ග堂瀀ꀏ會Āﶖ⨀〲岒ऀĀ᐀會Ā᐀䁇ﶖ⨀젲岒Ā㰀會Ā㰀顇ﶖ⨀끩Ā㈀會Ā㈀ﶖ⨀䡪Ā᐀會Ā᐀䡈ﶖ⨀Ā᐀會Ā᐀ꁈﶖ⨀硫Ā저會Ā저ﶖ⨀샟ගကĀ저會Ā저偉ﶖ⨀栰岒ఀĀ저會Ā저ꡉﶖ⨀1岒Ā저會Ā저Jﶖ⨀惝ග؀Ā؀會Ā؀塊ﶖ⨀ග㼀Ā切會Ā切끊ﶖ⨀⣟ගఀĀ搀會Ā搀ࡋﶖ⨀큭킢Ā저會Ā저

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.5
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• pp.519-525
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• 2015

Positive bias stress-induced instability in amorphous indium-gallium-zinc-oxide (a-IGZO) bottom-gate thin-film transistors (TFTs) was investigated under high $V_{GS}$/low $V_{DS}$ and low $V_{GS}$/high $V_{DS}$ stress conditions through incorporating a forward/reverse $V_{GS}$ sweep and a low/high $V_{DS}$ read-out conditions. Our results showed that the electron trapping into the gate insulator dominantly occurs when high $V_{GS}$/low $V_{DS}$ stress is applied. On the other hand, when low $V_{GS}$/high $V_{DS}$ stress is applied, it was found that holes are uniformly trapped into the etch stopper and electrons are locally trapped into the gate insulator simultaneously. During a recovery after the high $V_{GS}$/low $V_{DS}$ stress, the trapped electrons were detrapped from the gate insulator. In the case of recovery after the low $V_{GS}$/high $V_{DS}$ stress, it was observed that the electrons in the gate insulator diffuse to a direction toward the source electrode and the holes were detrapped to out of the etch stopper. Also, we found that the potential profile in the a-IGZO bottom-gate TFT becomes complicatedly modulated during the positive $V_{GS}/V_{DS}$ stress and the recovery causing various threshold voltages and subthreshold swings under various read-out conditions, and this modulation needs to be fully considered in the design of oxide TFT-based active matrix organic light emitting diode display backplane.