• Journal of the Korean Society for Precision Engineering
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• v.24 no.9
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• pp.103-109
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• 2007

LCD (Liquid Crystal Display) is widely used electronic product. It needs too many processes such as PECVD (Plasma Enhanced Vapor Deposition), Sputtering, Photo-lithography, Dry etch. Each process is important but inspection process is more important because most companies emphasis on the six sigma. Recently, LCD inspection system is composed with inlet, inspector, outlet air pads. LCD is inspected on air pad which is shooting air from air hole. This paper studies on pad design of air bearing for LCD inspection to minimize LCD fluctuation. This design is able to reduce fluctuation and then satisfies CCD inspectional range. Also inspection pad needs to adequate stable area.

• Journal of the Korean Society for Precision Engineering
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• v.22 no.9 s.174
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• pp.60-68
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• 2005

To investigate the effects of beam focusing in the etching of polymers with short pulse Excimer lasers, a polymer etching model of SSB's is combined with a beam focusing model. Through the numerical simulation, it was found that in the high laser fluence region, SSB model considering both photochemical and thermal contribution is considered to be suitable to predict the etched hole shape than a simple photochemical etching model. The average temperature distribution into the substance obtained by assuming 1-D heat transfer is found to be fairly similar to the fluence distribution on the ablated surface. The experimental etching data fur polymers are used to give material properties for ablation model. The fitted etch depth curve gives a nice agreement with the experimental data.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2002.05a
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• pp.74-78
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• 2002

MEMS공정을 이용하여 폴리실리콘의 piezoresistivity를 이용한 스트레인 센서어레이를 제작하였고, 이 센서 어레이를 flexible substrate에 패키징하는 공정을 개발하였다. 실리콘 웨이퍼에 표면 가공(surface micromachining)된 센서는 폴리이미드 코팅, release-etch 방법을 통해 웨이퍼로부터 분리되어 폴리이미드를 기판으로 하는 flexible sensor array module을 완성할 수 있었다. 공정은 희생층과 절연층을 증착하고 폴리실리콘 0.5 $\mu\textrm{m}$을 증착, 도핑 및 패터닝하여 센서 어레이를 구성하였다. 이 센서어레이를 flexible substrate에 패키징 하기 위해서 폴리이미드를 코팅하여 15 $\mu\textrm{m}$의 막을 구성하였고, 100% $O_2$RIE를 이용한 선택적 식각 방법으로 via hole을 구성하였다. 이후 전기도금을 통해 회로를 구성하여 1단계 패키징(die to chip carrier)과 2단계 패키징(chip to substrate)을 웨이퍼 레벨에서 완성하였다. 희생층을 제거함으로서 웨이퍼로부터 센서어레이 모듈을 분리하였다. 제작되어진 센서 모듈은 임의의 곡면에 실장이 가능하도록 충분한 flexibility를 얻을 수 있었다.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.5
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• pp.519-525
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• 2015

Positive bias stress-induced instability in amorphous indium-gallium-zinc-oxide (a-IGZO) bottom-gate thin-film transistors (TFTs) was investigated under high $V_{GS}$/low $V_{DS}$ and low $V_{GS}$/high $V_{DS}$ stress conditions through incorporating a forward/reverse $V_{GS}$ sweep and a low/high $V_{DS}$ read-out conditions. Our results showed that the electron trapping into the gate insulator dominantly occurs when high $V_{GS}$/low $V_{DS}$ stress is applied. On the other hand, when low $V_{GS}$/high $V_{DS}$ stress is applied, it was found that holes are uniformly trapped into the etch stopper and electrons are locally trapped into the gate insulator simultaneously. During a recovery after the high $V_{GS}$/low $V_{DS}$ stress, the trapped electrons were detrapped from the gate insulator. In the case of recovery after the low $V_{GS}$/high $V_{DS}$ stress, it was observed that the electrons in the gate insulator diffuse to a direction toward the source electrode and the holes were detrapped to out of the etch stopper. Also, we found that the potential profile in the a-IGZO bottom-gate TFT becomes complicatedly modulated during the positive $V_{GS}/V_{DS}$ stress and the recovery causing various threshold voltages and subthreshold swings under various read-out conditions, and this modulation needs to be fully considered in the design of oxide TFT-based active matrix organic light emitting diode display backplane.

• Journal of the korean academy of Pediatric Dentistry
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• v.45 no.4
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• pp.445-454
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• 2018

The aim of this study was to measure the shear bond strength (SBS) of different adhesive systems to calcium silicate-based materials (Biodentine and RetroMTA). Eighty cylindrical acrylic blocks, with a hole (5.0 mm diameter, 2.0 mm height) in each, were prepared. The holes were filled with Biodentine (BD) and RetroMTA (RMTA), and the specimens were divided into 2 groups. Each group was classified into 4 subgroups: Clearfil$^{TM}$ SE (CSE) ; AQ bond (AQ) ; All bond universal Self-etch (ABU-SE) ; and All bond universal Total-etch (ABU-TE). After the application of different adhesive systems, composite resin (Z350) was applied over BD and RMTA. The SBS was measured using a universal testing machine, and the data were compared using the Kruskal-Wallis test and the Mann-Whitney test. The highest and lowest values of SBS were observed for BD-ABU-SE and RMTA-AQ, respectively. No significant differences were found in the SBS between ABU-TE and ABU-SE and between ABU-TE and CSE to BD and RMTA. According to the data, BD showed a higher SBS than did RMTA when BD and RMTA are compared in the same adhesive agents. Further, among all groups, composite resin with ABU-SE showed better bond strength to BD and RMTA.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.2
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• pp.41-47
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• 1999

In this paper, we report 3D-simulations of a plasma etching process by employing cell-removal algorithm takes into account the mask shadow effect os well as spillover errors. The developed simulator haas an input interface to take not only an analytic form but a Monte Carlo distribution of the ions. The graphic user interface(GUI) was also built into the simulator for UNIX environment. To demonstrate the capability of 3D-SURFILER(SURface proFILER), we have simulated for a typical contact hole structure with 36,000($30{\times}40{\times}30$) cells, which takes about 20 minutes with 10 Mbytes memory on sun ultra sparc 1. as an exemplary case, we calculated the etch profile during the reactive ion etching(RIE) of a contact hole wherein the aspect ratio is 1.57. Furthermore, we also simulated the dependence of a damage parameter and the evolution of topography as a function of the chamber pressure and the incident ion flux.

• Journal of the Semiconductor & Display Technology
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• v.17 no.3
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• pp.36-40
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• 2018

We have developed a nonlithographic patterning technique using polystyrene nanoparticles to form nanonet channel structures which is promising for high-performance TFT applications. Nanoparticles assisted patterning (NAP) is a technique to form uniform nano-patterns by applying lift-off and dry etch process. Oxygen plasma treatment was used to control the diameters of nanonet hole size to realize a branch width down to 100 nm. NAP technology can be very promising to fabricate nanonet structure with advantages of lower manufacturing cost and large-area patterning capability.

• Korean Chemical Engineering Research
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• v.47 no.6
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• pp.715-719
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• 2009

The phase change electrode board for the bio-information detection through electrical property response of phase change material was developed in this study. We manufactured the electrode board using Aluminum first that is widely used in conventional semiconductor device process. Without further treatment, these aluminum electrodes tend to contain voids in PETEOS(plasma enhanced tetraethyoxysilane) material that are easily detected by cross-sectional SEM(Scanning Electron Microscope). The voids can be easily attacked and transformed into holes in between PETEOS and electrodes after etch back and washing process. In order to resolve this issue of Al electrode board, we developed a electrode board manufacturing method using low resistivity TiN, which has advantages in terms of the step-coverage of phase change($Ge_2Sb_2Te_5$, GST) thin film as well as thermodynamic stability, without etch back and washing process. This TiN material serves as the top and bottom electrode in PRAM(Phase-change Random Access Memory). The good connection between the TiN electrode and GST thin film was confirmed by observing the cross-section of TiN electrode board using SEM. The resistances of amorphous and crystalline GST thin film on TiN electrodes were also measured, and 1000 times difference between the amorphous and crystalline resistance of GST thin film was obtained, which is well enough for the signal detection.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.150-150
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• 2008

본 연구에서는 Wet chemistry damage가 Nanopatterned p-ohmic electrode에 미치는 영향을 연구하였다. Nanopattern은 Metal clustering을 이용하여, P-GaN와 Ohmic형성에 유리한 Pd을 50$\AA$ 적층한 후 Rapid Thermal Annealing방법으로 $850^{\circ}C$, $N_2$분위기에서 3min열처리를 하여 Pd Clustering mask 를 제작하였다. Wet etching은 $85^{\circ}C$, $H_3PO_4$조건에서 시간에 따라 Sample을 Dipping하는 방법으로 시행하였다 Ohmic test를 위해서 Circular - Transmission line Model 방법을 이용하였으며, Atomic Force Microscopy과 Parameter Analyzer로 Nanopatterned GaN surface위에 형성된 Ni/ Au Contact에서의 전기적 분석과, 표면구조분석을 시행하였다. AFM결과 Wet처리시간에 따라서 Etching형상 및 Etch rate이 영향을 받는 것이 확인되었고, Ohmic test에서 Wet chemistry처리에 의한 Tunneling parameter와 Schottky Barrier Height가 크게 증/감함을 관찰하였다. 이러한 결과들은 Wet처리에 의해서 발생된 Defect가 GaN의 표면과 하부에서 발생되며, Deep acceptor trap 및 transfer거동과 밀접한 관련이 있음을 확인 할 수 있었다. 보다 자세한 Transport 및 Wet chemical처리영향에 관한 형성 Mechanism은 후에 I-V-T, I-V, C-V, AFM결과 들을 활용하여 발표할 예정이다.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.4 no.1
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• pp.83-91
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• 1994

We have constructed a vertical gradient freeze (VGF) grower for GaAs single crystals 2 inch in diameter and have grown semi-insulating GaAs co-doped with Cr and In. For the co-doped crystal, the segregation coefficients of the dopants remain unchanged when compared to those doped with only Cr or In. The concentration of Cr and in atoms range from about $2{\Times}10_{16} to 3{imes}10^{17} cm^{-3}$ and $2{\Times}10^{19} to 3{\Times}10^{20} cm^{-3}$ at the seed to the tail part of the grown crystal, respectively. The averaged dislocation etch pit density is found to be less than $8000 cm^{-2}$ throughout the ingot. It is also found that there is some evidence of lattice hardening for the crystal in which the dislocation density is decreased to less than $1000 cm^{-2}$ as In concentration increases. The resistivity increases abruptly from $10^{-2}$ up to $10^8$ Ohm-cm, while the carrier concentration decreases from $10^{16}$ to $10^8 cm^{-3}$ along the growth direction of the GaAs crystal. Semi-insulating properties can be obtained above a critical concentration of Cr of about $6{\Times}10{^16} cm^{-3}$ in the crystal. The main deep levels existing in the GaAs: Cr,In sample are two electron traps at $E_C-0.81eV, E_C-0.35eV$, and two hole traps at $E_V+0.89eV, E_V+0.65eV$.