• Title/Summary/Keyword: Error-correction code

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Design and Implementation of e2eECC for Automotive On-Chip Bus Data Integrity (차량용 온칩 버스의 데이터 무결성을 위한 종단간 에러 정정 코드(e2eECC)의 설계 및 구현)

  • Eunbae Gil;Chan Park;Juho Kim;Joonho Chung;Joosock Lee;Seongsoo Lee
    • Journal of IKEEE
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    • v.28 no.1
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    • pp.116-122
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    • 2024
  • AMBA AHB-Lite bus is widely used in on-chip bus protocol for low-power and cost-effective SoC. However, it lacks built-in error detection and correction for end-to-end data integrity. This can lead to data corruption and system instability, particularly in harsh environments like automotive applications. To mitigate this problem, this paper proposes the application of SEC-DED (Single Error Correction-Double Error Detection) to AMBA AHB-Lite bus. It aims not only to detect errors in real-time but also to correct them, thereby enhancing end-to-end data integrity. Simulation results demonstrate real-time error detection and correction when errors occur, which bolsters end-to-end data integrity of automotive on-chip bus.

Optimum Inner and Outer Code Rates for Concatenated Codes in Gaussian Binary Symmetric Channels (가우시안 이진 대칭 채널에서 쇄상부호의 최적 내.외 부호율에 관한 연구)

  • Lee, Ye Hoon
    • Journal of Satellite, Information and Communications
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    • v.9 no.2
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    • pp.110-113
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    • 2014
  • In this paper, we address a problem of finding the optimum inner and outer code rates for a concatenated code in Gaussian binary symmetric channels. Clearly, as the inner code rate decreases, the error detection capability of the inner code increases. However, decreasing the inner code rate implies a decrease in error-correction capability of the outer code when overall code rate is fixed. With this notion in mind, we examine the optimum distribution of redundancy on the outer and inner codes to achieve a maximum performance gain in the concatenated coding scheme. Our analysis shows that the maximum coding gain can be obtained when the inner code rate is maximized and the outer code rate is minimized under the constraint of total code rate is fixed.

Study on Error Correction Method for Advanced Terrestrial DMB (고품질 지상파 DMB를 위한 오류정정방식 연구)

  • Choi, Gyoo-Seok;Jeon, Byung-Chan;Park, In-Kyoo
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.10 no.5
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    • pp.69-75
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    • 2010
  • Advanced T-DMB(Terrestial DMB )system which is a new portable mobile broadcasting system has been developed to increase data rate up to double of conventional T-DMB in same bandwidth while maintaining backward compatibility, using hierarchical modulation method. The Advanced T-DMB system realize high qualification of conventional T-DMB system by adding BPSK signal or QPSK signal as enhanced layer to existing DQPSK signal. The enhanced layer signal should be small enough to maintain backward compatibility and to minimize the coverage loss of existing T-DMB service area. But this causes the enhanced layer signal of Advanced T-DMB susceptible to fading effect in transmission channel. In this paper we applied the duo-binary turbo code which has powerful error correction capability to the enhanced layer signal for compensating channel distortion. And the computer simulation results about the performance of the duo-binary turbo code in Advanced T-DMB system are presented along with analysis comments.

LINEAR AND NON-LINEAR LOOP-TRANSVERSAL CODES IN ERROR-CORRECTION AND GRAPH DOMINATION

  • Dagli, Mehmet;Im, Bokhee;Smith, Jonathan D.H.
    • Bulletin of the Korean Mathematical Society
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    • v.57 no.2
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    • pp.295-309
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    • 2020
  • Loop transversal codes take an alternative approach to the theory of error-correcting codes, placing emphasis on the set of errors that are to be corrected. Hitherto, the loop transversal code method has been restricted to linear codes. The goal of the current paper is to extend the conceptual framework of loop transversal codes to admit nonlinear codes. We present a natural example of this nonlinearity among perfect single-error correcting codes that exhibit efficient domination in a circulant graph, and contrast it with linear codes in a similar context.

Novel construction of quasi-cyclic low-density parity-check codes with variable code rates for cloud data storage systems

  • Vairaperumal Bhuvaneshwari;Chandrapragasam Tharini
    • ETRI Journal
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    • v.45 no.3
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    • pp.404-417
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    • 2023
  • This paper proposed a novel method for constructing quasi-cyclic low-density parity-check (QC-LDPC) codes of medium to high code rates that can be applied in cloud data storage systems, requiring better error correction capabilities. The novelty of this method lies in the construction of sparse base matrices, using a girth greater than 4 that can then be expanded with a lift factor to produce high code rate QC-LDPC codes. Investigations revealed that the proposed large-sized QC-LDPC codes with high code rates displayed low encoding complexities and provided a low bit error rate (BER) of 10-10 at 3.5 dB Eb/N0 than conventional LDPC codes, which showed a BER of 10-7 at 3 dB Eb/N0. Subsequently, implementation of the proposed QC-LDPC code in a softwaredefined radio, using the NI USRP 2920 hardware platform, was conducted. As a result, a BER of 10-6 at 4.2 dB Eb/N0 was achieved. Then, the performance of the proposed codes based on their encoding-decoding speeds and storage overhead was investigated when applied to a cloud data storage (GCP). Our results revealed that the proposed codes required much less time for encoding and decoding (of data files having a 10 MB size) and produced less storage overhead than the conventional LDPC and Reed-Solomon codes.

High-Performance Low-Complexity Iterative BCH Decoder Architecture for 100 Gb/s Optical Communications (100 Gb/s급 광통신시스템을 위한 고성능 저면적 반복 BCH 복호기 구조)

  • Yang, Seung-Jun;Yeon, Jaewoong;Lee, Hanho
    • Journal of the Institute of Electronics and Information Engineers
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    • v.50 no.7
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    • pp.140-148
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    • 2013
  • This paper presents a iterative Bose-Chaudhuri-hocquenghem (i-BCH) code and its high-speed decoder architecture for 100 Gb/s optical communications. The proposed architecture features a very high data processing rate as well as excellent error correction capability. The proposed 6-iteration i-BCH code structure with interleaving method allows the decoder to achieve 9.34 dB net coding gain performance at $10^{-15}$ decoder output bit error rate to compensate for serious transmission quality degradation. The proposed high-speed i-BCH decoder architecture is synthesized using a 90-nm CMOS technology. It can operate at a clock frequency of 430 MHz and achieve a data processing rate of 100 Gb/s. Thus, it has potential applications in next generation forward error correction (FEC) schemes for 100 Gb/s optical communications.

A Study on Minimization Method of Reading Error Range and Implementation of Postal 4-state Bar Code Reader with Raster Beam (Raster Beam에 의한 우편용 4-state 바코드 판독기 구현 및 판독오차 범위의 최소화 방법에 관한 연구)

  • Park, Moon-Sung;Song, Jae-Gwan;Nam, Yun-Seok;Kim, Hye-Kyu;Jung, Hoe-Kyung
    • The Transactions of the Korea Information Processing Society
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    • v.7 no.7
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    • pp.2149-2160
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    • 2000
  • Recently many efforts on the development of automatic processing system for delivery sequence sorting have been performed in ETRI, which requires the use of postal4-state bar code system to encode delivery points. The 4-state bar code called postal 4-state barcode for high speed processing that has been specifically designed for information processing of logistics and automatic processing of he mail items. The Information of 4-state bar code indicates mail data such as post code, delivery sequence number, error correction code worked, customer information, and a unique ID. This appear addresses the issue on he reduction of reading error in postal 4-state raster beam based bar code reader. The raster beam scanning features are the unequally distributed number of spots per each unit, which cause reading errors. We propose a method for reducing the bar code reading error by adjusting measured values of bar code width to its average value over each interval. The test results show that the above method reduces the average reading error rate approximately by 99.88%.

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A Comparisons of TCM schemes for OFDM in fading channel (페이딩 채널에서 OFDM에 적용 가능한 TCM방식 비교분석)

  • 조기원;박범대
    • Proceedings of the IEEK Conference
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    • 1999.11a
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    • pp.79-82
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    • 1999
  • In this paper, it was studied that the performance of OFDM transmission scheme was improved in fading channel by applying TCM, which has advantages of error correction and bandwidth efficiency. Simulation was carried out for two TCM models with different code efficient length. By mapping two models to square 16QAM, the model with the code efficient length of 2 achieved 3㏈ better than the other for the BER of 10$^{-3}$ . In conclusion, if we want to achieve a better performance with TCM in OFDM applications, we should select a TCM with langer code efficient length.

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Search Methods for Covering Patterns of CRC Codes for Error Recovery (오류 복구를 위한 CRC 코드 커버링 패턴의 탐색 방법)

  • Sung, Won-Jin
    • Journal of Institute of Control, Robotics and Systems
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    • v.8 no.4
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    • pp.299-302
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    • 2002
  • Error detection and correction using CRC and the general class of cyclic codes is an important part of designing reliable data transmission schemes. The decoding method for cyclic codes using covering patterns is easily-implementable, and its complexity de-pends on the number of covering patterns employed. Determination of the minimal set of covering patterns for a given code is an open problem. In this paper, an efficient search method for constructing minimal sets of covering patterns is proposed and compared with several existing search methods. The result is applicable to various codes of practical interest.

Research Trends in Quantum Error Decoders for Fault-Tolerant Quantum Computing (결함허용 양자 컴퓨팅을 위한 양자 오류 복호기 연구 동향)

  • E.Y. Cho;J.H. On;C.Y. Kim;G. Cha
    • Electronics and Telecommunications Trends
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    • v.38 no.5
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    • pp.34-50
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    • 2023
  • Quantum error correction is a key technology for achieving fault-tolerant quantum computation. Finding the best decoding solution to a single error syndrome pattern counteracting multiple errors is an NP-hard problem. Consequently, error decoding is one of the most expensive processes to protect the information in a logical qubit. Recent research on quantum error decoding has been focused on developing conventional and neural-network-based decoding algorithms to satisfy accuracy, speed, and scalability requirements. Although conventional decoding methods have notably improved accuracy in short codes, they face many challenges regarding speed and scalability in long codes. To overcome such problems, machine learning has been extensively applied to neural-network-based error decoding with meaningful results. Nevertheless, when using neural-network-based decoders alone, the learning cost grows exponentially with the code size. To prevent this problem, hierarchical error decoding has been devised by combining conventional and neural-network-based decoders. In addition, research on quantum error decoding is aimed at reducing the spacetime decoding cost and solving the backlog problem caused by decoding delays when using hardware-implemented decoders in cryogenic environments. We review the latest research trends in decoders for quantum error correction with high accuracy, neural-network-based quantum error decoders with high speed and scalability, and hardware-based quantum error decoders implemented in real qubit operating environments.