• Journal of the Optical Society of Korea
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• 제20권5호
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• pp.623-627
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• 2016

A power-adjustable fully-integrated CMOS optical receiver with multi-rate clock-and-data recovery circuit is presented in standard 65-nm CMOS technology. With supply voltage scaling, key features of the optical receiver such as bandwidth, power efficiency, and optical sensitivity can be automatically optimized according to the bit rates. The prototype receiver has −23.7 dBm to −15.4 dBm of optical sensitivity for 10⁻⁹ bit error rate with constant conversion gain around all target bit rates from 1.62Gbps to 8.1 Gbps. Power efficiency is less than 9.3 pJ/bit over all operating ranges.

• 한국정보전자통신기술학회논문지
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• 제7권4호
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• pp.195-199
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• 2014

A bridge resistance deviation-to-period (BRD-to-P) converter is presented for interfacing resistive biosensors. It consists of a linear operational transconductance amplifier (OTA) and a current-controlled oscillator (CCO) formed by a current-tunable Schmitt trigger and an integrator. The free running period of the converter is 1.824 ms when the bridge offset resistance is $1k{\Omega}$. The conversion sensitivity of the converter amounts to $3.814ms/{\Omega}$ over the resistance deviation range of $0-1.2{\Omega}$. The linearity error of the conversion characteristic is less than ${\pm}0.004%$.

• Journal of Communications and Networks
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• 제11권3호
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• pp.229-239
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• 2009

Orthogonal frequency division multiplexing (OFDM) has been adopted as a standard for various high data rate wireless communication systems due to the spectral bandwidth efficiency, robustness to frequency selective fading channels, etc. However, implementation of the OFDM system entails several difficulties. One of the major drawbacks is the high peak-to-average power ratio (PAPR), which results in intercarrier interference, high out-of-band radiation, and bit error rate performance degradation, mainly due to the nonlinearity of the high power amplifier. This paper reviews the conventional PAPR reduction schemes and their modifications for achieving the low computational complexity required for practical implementation in wireless communication systems.

• Journal of Electrical Engineering and Technology
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• 제7권2호
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• pp.221-224
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• 2012

We propose a Readout Integrated Circuit (ROIC), which applies a fixed current bias sensing method to the input stage in order to simplify the circuit structure and the infrared sensor characteristic control. For the sample-and-hold stage to display and control a signal detected by the infrared sensor using a two-dimensional (2D) focal plane array, a differential delta sampling (DDS) circuit is proposed, which effectively removes the FPN. In addition, the output characteristic is improved to have wider bandwidth and higher gain by applying a two-stage variable gain amplifier (VGA). The output characteristic of the proposed device was 23.91 mV/$^{\circ}C$, and the linearity error rate was less than 0.22%. After checking the performance of the ROIC using HSPICE simulation, the chip was manufactured and measured using the SMIC 0.35 um standard CMOS process to confirm that the simulation results from the actual design are in good agreement with the measurement results.

• Journal of Power Electronics
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• 제13권6호
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• pp.991-999
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• 2013

In this paper, a fast transient buck converter using hysteresis PWM control is presented. The proposed control method is based on hysteresis control of the capacitor C voltage. This offers a faster transient response to meet the challenges of the power supply requirements for fast dynamic input and load changes. It also provides better stability and solves the compensation problem of the error amplifier in conversional voltage PWM control. Finally, the steady-state and dynamic operation of the proposed control method are analyzed and verified by simulation and experimental results.

• Current Optics and Photonics
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• 제2권6호
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• pp.519-524
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• 2018

We propose a transverse load sensor with reconfigurable measurement accuracy based on a microwave photonic filter in the $K_u$ band, incorporating a polarization-maintaining fiber Bragg grating. A prototype sensor with a reconfigurable measurement accuracy tuning range from 6.09 to 9.56 GHz/(N/mm), and corresponding minimal detectable load range from 0.0167 to 0.0263 N/mm, is experimentally demonstrated. The results illustrate that up to 40% manufacturing error in the grating length can be dynamically calibrated to the same corresponding measurement accuracy for the proposed transverse load sensor, by controlling the semiconductor optical amplifier's injection current in the range of 154 to 419 mA.

• 전기전자학회논문지
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• 제24권4호
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• pp.1162-1166
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• 2020

본 논문에서는 피드백 감지 회로 구조로 인하여 향상된 load regulation 특성을 개선시킨 LDO를 제안하였다. LDO 레귤레이터 내부 오차증폭기의 출력단과 패스 트랜지스터의 입력단 사이에 제안된 feedback 감지 회로를 추가하여 출력에 들어오는 델타 값의 regulation을 개선시켜 기존의 LDO 레귤레이터보다 개선된 load Regulation 특성의 전압 값을 갖는다. 제안된 회로는 Cadence의 Spectre, Virtuoso 시뮬레이션을 이용하여 삼성 0.13um 공정에서 특성을 시뮬레이션 하였다.

• ETRI Journal
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• 제46권4호
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• pp.595-603
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• 2024

This paper presents methods for reducing the peak-to-average power ratio (PAPR) of the orthogonal time frequency space (OTFS) signal. These methods mainly consist of two operations: symbol interferometry (SI) and either 𝜇-law or A-law companding. SI spreads the data of one OTFS symbol onto all symbols and is implemented using a simple inverse fast Fourier transform operation on each OTFS symbol. During the second operation, the PAPR of the OTFS signal is significantly reduced. For our performance analysis, the complementary cumulative distribution function, probability density function, and bit error rate are illustrated through simulations performed in MATLAB. The performance is also analyzed using a solid-state power amplifier at the transmitter and compared with OTFS, 𝜇-law-based OTFS, and SI OTFS systems. The results indicate that the proposed OTFS system achieves a low PAPR.

• Journal of information and communication convergence engineering
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• 제10권1호
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• pp.85-90
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• 2012

A 40-MS/sec 10-bit pipelined analog to digital converter (ADC) with a 1.2 Vpp differential input signal is proposed. The implemented pipelined ADC consists of eight stages of 1.5 bit/stage, one stage of 2 bit/stage, a digital error correction block, band-gap reference circuit & reference driver, and clock generator. The 1.5 bit/stage consists of a sub-ADC, digital to analog (DAC), and gain stage, and the 2.0 bit/stage consists of only a 2-bit sub-ADC. A bootstrapped switch with a constant resistance is proposed to improve the linearity of the input switch. It reduces the maximum VGS variation of the conventional bootstrapped switch by 67%. The proposed bootstrapped switch is used in the first 1.5 bit/stage instead of a sample-hold amplifier (SHA). This results in the reduction of the hardware and power consumption. It also increases the input bandwidth and dynamic performance. A reference voltage for the ADC is driven by using an on-chip reference driver without an external reference. A digital error correction with a redundancy is also used to compensate for analog noise such as an input offset voltage of a comparator and a gain error of a gain stage. The proposed pipelined ADC is implemented by using a 0.18-${\mu}m$ 1- poly 5-metal CMOS process with a 1.8 V supply. The total area including a power decoupling capacitor and the power consumption are 0.95 $mm^2$ and 51.5 mW, respectively. The signal-to-noise and distortion ratio (SNDR) is 56.15 dB at the Nyquist frequency, resulting in an effective number of bits (ENOB) of 9.03 bits.

• 한국전자파학회논문지
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• 제15권12호
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• pp.1184-1189
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• 2004

본 논문에서는 직교신호를 발생할 수 있는 새로운 구조의 전압제어 발진기를 설계 제작하였다. 정확한 직교 신호 특성과 낮은 위상잡음 특성을 동시에 얻기 위하여 결합 증폭기의 source단자에 저항 궤환을 이용하여 차동 발진기를 결합시켰다. 발진기는 0.18 um 표준 CMOS 공정을 이용하여 제작하였다. 제작한 발질기의 위상잡음 특성은 -120 dBc/Hz @ 1 MHz 0$\~$1.8 V 전압을 가변하였을 때, 2.34 GHz$\~$2.55 GHz의 210 MHz 주파수 가변을 얻었다. 또한 낮은 IF 주파수 혼합기와 결합하여 측정한 결과 직교신호의 위상 오차는 0.5도, 진폭 오차는 0.2 dB 이하를 보였다. 바이어스 전류는 1.8 V 공급전압에 대해 전압제어발진기의 Core 부분 5 mA를 포함하여 전체적으로는 19 mA를 요구한다.