• The Journal of Korean Institute of Communications and Information Sciences
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• v.40 no.9
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• pp.1693-1698
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• 2015

This paper proposed a PFM(pulse-frequency modulator) boost converter which has dual pulse-width. The PFM boost converter is composed of BGR(band gap voltage reference generating circuit), voltage reference generating circuit, soft-start circuit, error amplifier, high-speed comparator, inductor current sensing circuit and pulse-width generator. Converter has different inductor peak current so it has wider load current range and smaller output voltage ripple. Proposed PFM boost converter generates 18V output voltage with input voltage of 3.7V and it has load current range of 0.1~300mA. Simulation results show 0.43% output voltage ripple at ligh load mode and 0.79% output voltage ripple at heavy load mode. Converter has efficiency 85% at light lode mode and it has maximum 86.4% at 20mA load current.

• 전자공학회논문지 IE
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• v.43 no.1
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• pp.16-24
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• 2006

This paper is aimed to develope of an integrated BCI(Brain Computer Interface System) that make possible for simultaneous multichannel data process and used extra cellular neural activity from the vestibular system instead of electroencephalogram signals for more precision control. The electrical properties pre-amplifier are 47.6 dB of gain, 0.005 % of distortion at 100 Hz, 12M$\Omega$ of input impedance. Window discriminator used two CPU with difference role to increase processing speed so that sampling frequency was 87 kHz. The designed window discriminator has more not only two times in signal resolution power but also ten times in error discrimination power than commericially available discriminator. The proposed method decreases 100 times in amount of integrated data then BCI system during 100 ms.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.43 no.5 s.311
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• pp.28-35
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• 2006

This paper presents a new 3.3-1 V synchronous buck DC/DC converter that employs CMOS operational transconductance amplifiers (OTAs) as circuit-building blocks. An error amplifier OTA in a PWM circuit is compensated for to improve temperature stability. The temperature coefficient of the transconductance gain of the compensated OTA is less than $150\;ppm/^{\circ}C\;over\;0-100^{\circ}C$. The HSPICE simulation results of the $0.3{\mu}m$ standard CMOS technology show that the efficiency of the proposed converter is as high as 80% in the load current range of 40-125 mA. These results show that the proposed converter is adequate for use in battery-operated systems.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.16 no.1
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• pp.627-633
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• 2015

We designed of a LDO regulator with a OVP and UVLO protection function for a PMIC. Proposed LDO regulator circuit consists of a BGR reference circuit, an error amplifier and a power transistor and so on. The proposed LDO regulator is designed for low voltage input power protection. Proposed LDO circuit generated fixed 2.5 V from a supply of 3.3V. It was designed with 3.3 V power supply using a $0.35{\mu}m$ CMOS technology. SPICE simulation results showed that the proposed circuit provides 0.713 mV/V line regulation with output 2.5 V ~ 3.9 V and $8.35{\mu}V/mA$ load regulation with load current 0 mA to 40 mA.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.5A
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• pp.484-492
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• 2006

A multi-code biorthogonal code keying(MBCK) system consists of multiple waveform coding block, and the sum of output codewords is transmitted. Drawback of MBCK is that it requires amplifier with high linearity because its output symbol is multi-level. MBCK with constant amplitude preceding blcok(CA-MBCK) has been proposed, which guarantees sum of orthogonal codes to have constant amplitude. Redundant bits of CA-MBCK for constant amplitude coding are not only used to make constant amplitude signal but also used to improve the bit error rate(BER) performance at receiver. In this paper, we proposed a transmission scheme which combine CA-MBCK with $Q^{2}PSK$ to improve bandwidth efficiency of CA-MBCK. The BER performance of the scheme is same that of CA-MBCK in additive white gaussian noise(AWGN). And we showed that BER performance of the proposed system can be improved using redundant bits of constant amplitude preceding.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.46 no.1
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• pp.43-48
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• 2009

We constructed a simple wavelength readout system for a tunable fiber laser which was used for a fiber Bragg grating sensor array system. A quadrature sampling method was used to demodulate wavelength variations of the tunable laser which consisted of a SOA(semi-conductor optical amplifier) and a fiber-optic Fabry-Perot filter. Internal triggers, which have a 90 degree phase period, have been generated by using a double-pass Mach-Zehnder interferometer. From Lissajous plots with quadrature sampled data, a mean phase error of ${\sim}2.51$ mrad was obtained. From the wavelength readout experiments, an accurate and fast linear wavelength demodulation has been confirmed.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.9
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• pp.1-7
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• 2008

This paper proposes 3.3V input and 1.8V output voltage mode step-down DC-DC buck converter for wireless mobile system which is designed in a standard 0.35$\mu$m CMOS process. The proposed capacitor multiplier method can minimize error amplifier compensation block size by 30%. It allows the compensation block of DC-DC converter be easily integrated on a chip. Also, we improve efficiency to 3% using low power buffer. Measurement result shows that the circuit has less than 1.17% output ripple voltage and maximum 83.9% power efficiency.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.05a
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• pp.143-146
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• 2011

A 50-MS/s 10-bit pipelined ADC with 1.2Vpp differential input range is proposed in this paper. The designed pipelined ADC consists of eight stage of 1.5bit/stage, one stage of 2bit/stage, digital error correction block, bias & reference driver, and clock generator. 1.5bit/stage is consists of sub-ADC, DAC and gain stage, Specially, a sample-and hold amplifier (SHA) is removed in the designed pipelined ADC to reduce the hardware and power consumption. Also, the proposed bootstrapped switch improves the Linearity of the input analog switch and the dynamic performance of the total ADC. The reference voltage was driven by using the on-chip reference driver without external reference. The proposed pipelined ADC was designed by using a 0.18um 1-poly 5-metal CMOS process with 1.8V supply. The total area including the power decoupling capacitor and power consumption are $0.95mm^2$ and 60mW, respectively. Also, the simulation result shows the ENOB of 9.3-bit at the Nyquist sampling rate.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.8A
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• pp.583-591
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• 2009

OFDM(orthogonal frequency division multiplexing) signal with high PAPR(peak to average power ratio) produces the nonlinear distortion and/or decreases down the power efficiency of HPA(high power amplifier). So, the IMD(inter-modulation distortion) reduction method was proposed to reduce the nonlinear distortion, which shows better BER(bit error rate) performance than the PAPR reduction methods. However, IMD reduction method has inherent problem which system complexity and processing time increases because the FFT(fast Fourier transform) processor is added in transmitter and decision criterion of IMD reduction method is computed in frequency domain,. In this paper, therefore, we propose a new IMD reduction method to reduce the computational complexity and structure of IMD computation. And we apply this proposed method into OFDM system using PTS(partial transmit sequence) scheme and compare the computational complexity between conventional and proposed IMD reduction method. This method can reduce the system size and computational complexity. Also, the proposed has almost same BER performance with the conventional IMD reduction method.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.10
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• pp.239-244
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• 2013

This paper presents a design of the CMOS LDO regulator with a UVLO protection function for a high speed PMIC. Proposed LDO regulator circuit consists of a BGR reference circuit, an error amplifier and a power transistor and so on. UVLO block between the power transistor and the power supply is added for a low input protection function. Also, UVLO block showed normal operation with turn-off voltage of 2.7V and turn-on voltage of 4 V in condition of 5 V power supply. Proposed circuit generated fixed 3.3 V from a supply of 5V. From SPICE simulation results using a $1{\mu}m$ high voltage CMOS technology, simulation results were 5.88 mV/V line regulation and 27.5 uV/mA load regulation with load current 0 mA to 200 mA.