• The Journal of Korean Institute of Communications and Information Sciences
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• v.14 no.4
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• pp.374-387
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• 1989

The decoding method of Binary BCH Codes using symmetric matrix is proposed in this paper. With this method, the error-locator-polynomial is composed by symmetric matrix which consists of the powers of the unknown X plus the synfromes as its elements. The symmetric matirx can also be represented in terms of the unknown X. But the each coefficients of the error-locator polynomial represents the matirx with the syndromes as its entries. By utilizing this proposed algorithm, the device for decoding circuit of the (63, 45) BCH Code for t=3 has been implemented for demonstration.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.679-682
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• 1998

This paper presents the VLSI implementation of RS(reed-solomon) decoder using the Modified Euclidean Algorithm(hereafter MEA) for DVD(Digital Versatile Disc) and CD(Compact Disc). The decoder has a capability of correcting 8-error or 16-erasure for DVD and 2-error or 4-erasure for CD. The technique of polynomial evaluation is introduced to realize syndrome calculation and a polynomial expansion circuit is developed to calculate the Forney syndrome polynomial and the erasure locator polynomial. Due to the property of our system with buffer memory, the MEA architecture can have a recursive structure which the number of basic operating cells can be reduced to one. We also proposed five criteria to determine an uncorrectable codeword in using the MEA. The overall architecture is a simple and regular and has a 4-stage pipelined structure.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.1C
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• pp.8-13
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• 2006

A new RS(Reed Solomon) Decoder design method, using Galois Subfield GF($2^4$) Multiplier, is described. The Decoder is designed using Normalized error position stored ROM. Here New Inverse Calculator in GF($2^8$) is designed, which is simpler and faster than the classical GF($2^8$) direct inverse calculator, using the Galois Subfield GF($2^4$) Arithmatic operator.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 1986.10a
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• pp.92-102
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• 1986

In this paper, Modular cell approach was applied to custom IC design or RS decoder. For the design of RS decoder by modular cells, 3 basic cells and one extra circuit are designed, these are, SYN cell for syndrome calculation, AL cell for error locator polynomial calculation, and REM cell for remaining error transform calculation. RS decoder design by these basic cells is very simple and regular, and naturally suitable for VLSI RS decoder design.

• Proceedings of the KIEE Conference
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• 1988.07a
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• pp.203-206
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• 1988

Direct Decoding Method for binary BCH codes which directly can find error location number from syndrome without calculating error locator polynomial is presented in this paper. The (255,239) BCH decoder is implemented using TTL logics. It is shown from our results that this decoder can be implemented with relatively simple hardware.

• Proceedings of the KIEE Conference
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• 1988.07a
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• pp.165-167
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• 1988

In this paper, the design of decoder for R-S code using discrete finite-field Fourier transform is presented. An important ingredient of this design is a modified Euclid algorithm for computing the error-locator polynomial. The computation of inverse elements is completely avoided in this modification of Euclid algorithm. This decoder is regular and simple, and naturally suitable for VLSI implementation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.8A
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• pp.1238-1244
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• 1999

In this paper, a new design of a triple-erroe-correcting (TEC) Reed-Solomon decoder is presented based on direct decoding method which is more efficient for the case of relatively small error correction capability. The proposed decoder requires only 9 GF(2m) multipliers in obtaining the error-locator polynomial and the error-evaluator polynomial, whereas other decoders needs 24 multipliers. Thus, the attractive feature of this decoder is its remarkable simplicity from the point of view of implementation. Futhermore, the proposed TEC Reed-Solomon decoder has very simple control circuit and short decoding delay. Therefore this decoder can be implemented by simple hardware and also save buffer memory which stores received sequence.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.4C
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• pp.191-196
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• 2011

In this paper, we propose a design method of Reed-Solomon (23, 17) decoder for UWB using direct decoding method. The direct decoding algorithm is more efficient for the case of relatively small error correction capability. The proposed decoder requires only 9 $GF(2^m)$ multipliers in obtaining the error-locator polynomial and the error-evaluator polynomial, whereas other decoders need about 20 multipliers. Thus, the attractive feature of this decoder is its remarkable simplicity from the point of view of hardware implementation. Futhermore, the proposed decoder has very simple control circuit and short decoding delay. Therefore this decoder can be implemented by simple hardware and also save buffer memory which stores received sequence.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.42 no.11
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• pp.13-20
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• 2005

For Modern Consumer and Communication Elecronic Devices, Always Error Protecting HW and SW is used. The Core is RS(Reed Solomon) Codec in Galois Field GF($2^8$). Here New 2 to 3 Symbol RS Decoder Design and Encoder design Method using Normalized error position Value is described. Examples are given to show the methods are working well.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.3 s.357
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• pp.61-67
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• 2007

In Reed Solomon decoder, when there are more than 4 error symbols, we usually use Chien search machine to find those error positions. In this case, classical method requires complex and relatively slow digital circuitry to implement it. In this paper we propose New fast and cost effective Chien search machine design method using Galois Subfield transformation. Example is given to show the method is working well. This new design can be applied to the case where there are more than 5 symbol errors in the Reed-Solomon code word.