• ETRI Journal
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• v.30 no.6
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• pp.799-806
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• 2008

In this paper, a new design for an error correcting code (ECC) is proposed. The design is aimed to build an ECC circuitry with minimal power consumption. The genetic algorithm equipped with the symbiotic mechanism is used to design a power-efficient ECC which provides single-error correction and double-error detection (SEC-DED). We formulate the selection of the parity check matrix into a collection of individual and specialized optimization problems and propose a symbiotic evolution method to search for an ECC with minimal power consumption. Finally, we conduct simulations to demonstrate the effectiveness of the proposed method.

• Proceedings of the Korean Society of Marine Engineers Conference
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• 2000.11a
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• pp.123-134
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• 2000

In this study, adapted Turbo Coding Algorithm for reducing communication error of fire detection system for marine vessels, especially image transmission. and proposed decoding speed increasing method of Turbo Coding Algorithm. The results are as follows : 1) Confirmed that a Turbo Code is so useful methods for reducing communication error in lots of noise environments. 2) Proposed technology in this study of speed increasing method of Turbo Coding Algorithm proved 2 times speed up effect than normal Turbo Code and communication error reducing as well in the board made by VHDL software & chips of ALTER Company.

• The KIPS Transactions:PartC
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• v.11C no.1
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• pp.109-114
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• 2004

A new code and its decoding scheme are proposed. With this code, we can correct and detect the errors in communication systems. To limit the runlength of data 0 and augment the minimum density of data 1, a (15, 7) BCH code is modified and an overall parity bit is added. The proposed code is a (16, 7) block code which has the bit clock signal regeneration capability and high error control capability. It is proved that the runlength of data 0 is less than or equal to 7, the density of data 1 is greater than or equal to 1/8, and the minimum Hamming distance is 6. The decoding error probability, the error detection probability and the correct decoding probability are presented for the proposed code. It is shown that the proposed code has better error control capability than the conventional schemes.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.10
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• pp.1559-1562
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• 2022

As electronic devices technology scales down into the deep-submicron to achieve high-density, low power and high performance integrated circuits, multiple bit upsets by soft errors have become a major threat to on-chip memory systems. To address the soft error problem, single error correction, double error detection and double adjacent error correction (SEC-DED-DAEC) codes have been recently proposed. But these codes do not troubleshoot mis-correction problem. We propose the SEC-DED_DAEC code with without mis-correction. The decoder for proposed code is implemented as hardware and verified. The results show that there is no mis-correction in the proposed codes and the decoder can be employed on-chip memory system.

• Journal of the Korea Institute of Military Science and Technology
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• v.14 no.4
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• pp.648-654
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• 2011

We can model marine uplink channel environment as time-correlated rician fading channel that has direct path and time varying reflected path. In this channel, error performance of uncoded system can be seriously degraded by multipath inteference. In this paper, we propose Concatenated Zigzag(CZZ) coded binary FSK signaling with noncoherent detection to improve error performance of uplink data in marine environment. CZZ code is a kind of channel coding scheme that is fast decodable as well as fast encodable. We have confirmed error performance of uplink data in marine environment can be improved dramatically through applying CZZ code.

• Proceedings of the IEEK Conference
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• 2000.11a
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• pp.77-80
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• 2000

Adaptive filter based code acquisition scheme offers a fast acquisition with a low error probability. However, it has been studied only under a coherent environment. In this paper, the noncoherent adaptive code acquisition scheme employing a differential detection technique is proposed. For the proposed scheme, system probabilities and the mean acquisition time are analyzed numerically. Simulation results show that the proposed system outperforms over the conventional matched filter by 2-4 ㏈ under AWGN channel for 16 taps.

• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.106-109
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• 2002

In the integrated systems, that is integrated digital TV(DTV) internet and home automation, like home server, is needed integration of digital TV video signal and computer graphic signal. The graphic signal is operating at the high speed and has time-divide-stream. So the re-request of data is not easy at the time of error detection. therefore EDAC algorithm is efficient. This paper presents the efficiency error detection auto correction(EDAC) for conversion of graphics signal to DTV video signal. A presented EDAC algorithms use the modified Hamming code for enhancing video quality and reliability. A EDAC algorithm of this paper can detect single error, double error, triple error and more error for preventing from incorrect correction. And it is not necessary an additional memory. In this paper The comparison between digital TV video signal and graphic signal, a EBAC algorithm and a design of conversion graphic signal to DTV signal with EDAC function is described.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.14 no.6
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• pp.590-603
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• 1989

In tnis paper, the CRC-CCITT code and primitive polynomial CRC code are selected for analysing error detecting performance. However, general formulas for obtaining the weight distribution of these two CRC codes are not so far dericed. So, a new method for calculating the weight distribution of the shortened cyclic Hamming code is presented and an undetected error probability of these two codes is obtained when used in cell of ATM for broadband ISDN user-network interface. Consequently, we show that CRC code too much does affect its error detection performance. All the computer simulation is performed by IBM PC/AT.

• Journal of IKEEE
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• v.18 no.4
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• pp.509-516
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• 2014

CRC feature in a high-speed semiconductor memory devices such as DDR4/GDDR5 increases the data reliability. Conventional CRC method have a massive area overhead and long delay time. It leads to insufficient internal timing margins for CRC calculation. This paper, presents a CRC code method that provides error detection and a real-time matrix type CRC. If there are errors in the data, proposed method can alert to the system in a real-time manner. Compare to the conventional method(XOR 6 stage ATM-8 HEC code), the proposing method can improve the error detection circuits up to 60% and XOR stage delay by 33%. Also the real-time error detection scheme can improve the error detection speed to agerage 50% for the entire data bits(UI0~UI9).

• Journal of IKEEE
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• v.21 no.2
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• pp.130-135
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• 2017

Normally, in data transmission, extra parity bits are added to the input message which were derived from its input and a pre-defined algorithm. The same algorithm is used by the receiver to check the consistency of the delivered information, to determine if it is corrupted or not. It recovers and compares the received information, to provide matching and correcting the corrupted transmitted bits if there is any. This paper aims the following objectives: to use an alternative error detection-correction method, to lessens both the fixed number of the required redundancy bits 'r' in cyclic redundancy checking (CRC) because of the required polynomial generator and the overhead of interspersing the r in Hamming code. The experimental results were synthesized using Xilinx Virtex-5 FPGA and showed a significant increase in both the transmission rate and detection of random errors. Moreover, this proposal can be a better option for detecting and correcting errors.