• The Journal of the Korea institute of electronic communication sciences
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• v.13 no.4
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• pp.721-728
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• 2018

This paper introduces various linear block error correction code and compares performances of the correction circuits. As the risk of errors due to power noise has increased, ECC(: Error Correction Code) has been introduced to prevent the bit error. There are two representatives of ECC structures which are SEC-DED(: Single Error Correction Double Error Detection) and SEC-DED-DAEC(: Double Adjacent Error Correction). According to simulation results, the SEC-DED circuit has advantages of small area and short delay time compared to SEC-DED-DAEC circuits. In case of SED-DED-DAEC, there is no big difference between Dutta's and Pedro's from performance point of view. Therefore, Pedro's code is more efficient than Dutta' code since the correction rate of Pedro's code is higher than that of Dutta's code.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.4
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• pp.418-425
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• 2012

In this paper, efficient implementation of error correction code (ECC) processing circuits based on single error correction and double error detection (SEC-DED) code with check bit pre-computation is proposed for memories. During the write operation of memory, check bit pre-computation eliminates the overall bits computation required to detect a double error, thereby reducing the complexity of the ECC processing circuits. In order to implement the ECC processing circuits using the check bit pre-computation more efficiently, the proper SEC-DED codes are proposed. The H-matrix of the proposed SEC-DED code is the same as that of the odd-weight-column code during the write operation and is designed by replacing 0's with 1's at the last row of the H-matrix of the odd-weight-column code during the read operation. When compared with a conventional implementation utilizing the odd-weight- column code, the implementation based on the proposed SEC-DED code with check bit pre-computation achieves reductions in the number of gates, latency, and power consumption of the ECC processing circuits by up to 9.3%, 18.4%, and 14.1% for 64 data bits in a word.

• Journal of the Semiconductor & Display Technology
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• v.19 no.3
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• pp.112-117
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• 2020

NAND flash memory is a non-volatile memory that retains stored data even without power supply. Internal memory used as a data storage device and solid-state drive (SSD) is used in portable devices such as smartphones and digital cameras. However, NAND flash memory carries the risk of electric shock, which can cause errors during read/write operations, so use error correction codes to ensure reliability. It efficiently recovers bad block information, which is a defect in NAND flash memory. BBT (Bad Block Table) is configured to manage data to increase stability, and as a result of experimenting with the error correction code algorithm, the bit error rate per page unit of 4Mbytes memory was on average 0ppm, and 100ppm without error correction code. Through the error correction code algorithm, data stability and reliability can be improved.

• Journal of the Korea Institute of Military Science and Technology
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• v.8 no.3 s.22
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• pp.42-50
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• 2005

In this paper, a novel method is proposed how the ECC(Error Correction Code) in server system can be investigated and the robustness of each system against noisy environment and element failure in memory module has been verified. Chipset manufacturers have hided the algorithm of their Hamming code and the user has difficulty in verification of the robustness of each system. The proposed method is very simple, but the outputs of the experiment explain the core ability of error correction in server system and helps the detection of the failure element. On the basis of these results, we could expect the robustness of digitalized weapon system and the efficient design of our own error correction code.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.10
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• pp.1559-1562
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• 2022

As electronic devices technology scales down into the deep-submicron to achieve high-density, low power and high performance integrated circuits, multiple bit upsets by soft errors have become a major threat to on-chip memory systems. To address the soft error problem, single error correction, double error detection and double adjacent error correction (SEC-DED-DAEC) codes have been recently proposed. But these codes do not troubleshoot mis-correction problem. We propose the SEC-DED_DAEC code with without mis-correction. The decoder for proposed code is implemented as hardware and verified. The results show that there is no mis-correction in the proposed codes and the decoder can be employed on-chip memory system.

• Proceedings of the IEEK Conference
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• 2001.09a
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• pp.239-242
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• 2001

영상에 워터마크를 삽입하는 것을 통신채널의 입장에서 해석한다면 워터마크는 신호로, 영상은 잡음으로 모델링이 가능하다. 따라서 이러한 잡음 속에서 신호에 대한 에러를 최소화하는 것이 워터마크의 추출을 최대화하는 것이라 할 수 있다. 통상적으로 Error Correction Code는 에러가 많은 통신채널에서 많이 이용되기 때문에 워터마킹 방법에서도 효과를 기대할 수 있다. 본 논문에서는 DCT 기반의 구간화 워터마킹 방법에 Turbo code를 이용하여 강인성 면에서의 향상된 성능을 실험 결과로 보이며, Turbo code의 해밍거리를 이용하여 워터마킹의 보다 효율적인 검출 방법을 제안한다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.11
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• pp.1747-1750
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• 2022

As shrinking the semiconductor process into the deep sub-micron to achieve high-density, low power and high performance integrated circuits, MBU (multiple bit upset) by soft errors is one of the major challenge of on-chip memory systems. To address the MBU, single error correction, double error detection and double adjacent error correction (SEC-DED-DAEC) codes have been recently proposed. But these codes do not resolve mis-correction. We propose the SEC-DED-DAEC-TAED(triple adjacent error detection) code without mis-corrections. The generated H-matrix by the proposed heuristic algorithm to accomplish the proposed code is implemented as hardware and verified. The results show that there is no mis-correction in the proposed codes and the 2-stage pipelined decoder can be employed on-chip memory system.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.5
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• pp.912-919
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• 1994

A new error control line code based on an extended Hamming code is proposed and its performance is analyzed in this paper. The proposed code is capable of single error correction and double error detection since its minimum Hamming distance is 4. In addition, the error detection capability can be oncreased due to the redundancy bit used for line coding. As a result, the proposed code shows lower code rate, but better spectral characteristics in low frequency region and lower residual bit error rate than the conventional error correction line code using Hamming (7, 4) code.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.7 no.10
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• pp.2527-2543
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• 2013

A novel steganographic QR code algorithm, which not only coveys the secret into the widely-used QR barcode but also preserves the readability of QR content and the capability of error correction, is presented in this article. Different from the conventional applications for QR barcode, the designed algorithm conceals the secret into the QR modules directly by exploiting the error correction capability. General browsers can read the QR content from the QR code via barcode readers; however, only the authorized receiver can further reveal the secret from the QR code directly. The new mechanism can convey a larger secret payload along with adjustment of the QR version and error correction level. Moreover, the blind property allows the receiver to reveal the secret without the knowledge of the embedded position of modules. Experimental results demonstrate that the new algorithm is secure, efficient and feasible for the low-power QR readers and mobile devices.

• Journal of the Korea Computer Industry Society
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• v.2 no.6
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• pp.791-802
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• 2001

In this paper, DARC(Data Radio Channel) error correction decoder for the U Subcarrier Broadcasting System is designed of using (272,190)$\times$(272,190) product code based on (272,190) shortened difference set cyclic code. This decoder has error flag of column and row direction that can store the result of the error correction of column and row direction in the block and frame structure, is designed to be of no benefit the output with majority logic determination to cancel the corrected and determined bit, and can improve by using the error correction method that no error correction of the row direction is performed, if error correction of the column direction is completely performed by error flag.