• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 1998.10a
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• pp.560-567
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• 1998

This paper concerned about a imputed color printed material image in camera to decrease noise and distortion by processing median filtering with input image to identical condition. Also this paper proposed the way of compares a normal printed material with an abnormal printed material color tone with trained a learning of the error back-propagation to block classification by extracting five place from identical block(3${\times}$3) of color printed material R, G, B value. As a representative algorithm of multi-layer perceptron the error Back-propagation technique used to solve complex problems. However, the Error Back-propagation is algorithm which basically used a gradient descent method which can be converged to local minimum and the Back Propagation train include problems, and that may converge in a local minimum rather than get a global minimum. The network structure appropriate for a given problem. In this paper, a good result is obtained by improve initial condition and adjust th number of hidden layer to solve the problem of real time process, learning and train.

• Journal of the Korea Computer Industry Society
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• v.3 no.5
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• pp.595-604
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• 2002

In this paper, we designed the encryption algorithm which protects ciphertext from deciphering solve the problem that it can pass the incorrect meaning. The algorithm checks the error of ciphertext during deciphering, and then if there are some errors of more than one bit. It stops the deciphering sequence and it doesn't pass any contents to receiver by removing the deciphering contents which was already done. The experiment compared with DES algorithm that is representative algorithm of secret key. As the result of experiment, the part that error bit was included with was deciphered to one that was different from plaintext, but it showed 100% decipher_rate. by the algorithm showed decipher_rate of 0% with deciphering through the error check.

• Journal of the Korean Society of Industry Convergence
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• v.4 no.2
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• pp.141-147
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• 2001

This paper presents a developing algorithm of checking errors of feed mechanism in the NC machine tool with DAC method. It is useful to check static and dynamic rigidity with relation between lost motion and current of rotor. For checking error of feed in assembly tuning with machining center proposed checking algorithm is useful.

• Journal of Electrical Engineering and information Science
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• v.2 no.6
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• pp.1-6
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• 1997

The scheduling problem of satisfying both 0/1 constraint and the timing constraint while minimizing the total error is NP-complete when the optional parts have arbitrary processing times. In this paper, we present a heuristic scheduling algorithm for 0/1 constraint imprecise systems which consist of communicating tasks running on multiple processors. The algorithm is based on the program graph which is similar to the one presented in[4]. To check the schedulability, we apply Lawler and Moore's theorem. To analyze the performance of the proposed algorithm, intensive simulation is done. The results of the simulation shows that the longest processing first selection strategy outperforms random or minimal laxity policies.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.10
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• pp.2143-2149
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• 2012

DVB-S2 employs LDPC codes which approach to the Shannon's limit, since it has characteristics of a good distance, error floor does not appear. Furthermore it is possible to processes full parallel processing. However, it is very difficult to high speed decoding because of a large block size and number of many iterations. This paper present HSS algorithm to reduce the iteration numbers without performance degradation. In the flooding scheme, the decoder waits until all the check-to-variable messages are updated at all parity check nodes before computing the variable metric and updating the variable-to-check messages. The HSS algorithm is to update the variable metric on a check by check basis in the same way as one code draws benefit from the other. Eventually, LDPC decoding speed based on HSS algorithm improved 30% ~50% compared to conventional one without performance degradation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.9A
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• pp.1101-1107
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• 2004

This paper presents an optimization algorithm and technique for designing parallel Cyclic Redundancy Check (CRC) circuit, which is most widely adopted for error detection A new heuristic algorithm is developed to find as many shared terms as possible, thus eventually to minimize the number and level of the exclusive-or logic blocks in parallel CRC circuits. 16-bit and 32-bit CRC generators are designed with different types of Programmable Logic Devices, and it has been found that our new algorithm and architecture significantly reduce the delay.

• Journal of Communications and Networks
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• v.15 no.1
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• pp.71-76
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• 2013

A new class of quantum low-density parity-check (LDPC) codes whose parity-check matrices are dual-containing matrices constructed based on lines of Euclidean geometries (EGs) is presented. The parity-check matrices of our quantum codes contain one and only one 4-cycle in every two rows and have better distance properties. However, the classical parity-check matrix constructed from EGs does not satisfy the condition of dual-containing. In some parameter conditions, parts of the rows in the matrix maybe have not any nonzero element in common. Notably, we propose four families of fascinating structure according to changes in all the parameters, and the parity-check matrices are adopted to satisfy the requirement of dual-containing. Series of matrix properties are proved. Construction methods of the parity-check matrices with dual-containing property are given. The simulation results show that the quantum LDPC codes constructed by this method perform very well over the depolarizing channel when decoded with iterative decoding based on the sum-product algorithm. Also, the quantum codes constructed in this paper outperform other quantum codes based on EGs.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.10a
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• pp.405-409
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• 2009

In this paper, the effects of LLR (Log-Likelihood Ratio) approximation on LDPC (Low-Density Parity-Check) decoder performance are analyzed, and optimal design conditions of LDPC decoder are derived. The min-sum LDPC decoding algorithm which is based on an approximation of LLR sum-product algorithm is modeled and simulated by MATLAB, and it is analyzed that the effects of LLR approximation bit-width and maximum iteration cycles on the bit error rate (BER) performance of LDCP decoder. The parity check matrix for IEEE 802.11n standard which has block length of 1,944 bits and code rate of 1/2 is used, and AWGN channel with QPSK modulation is assumed. The simulation results show that optimal BER performance is achieved for 7 iteration cycles and LLR bit-width of (7,5).

• ETRI Journal
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• v.36 no.1
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• pp.171-174
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• 2014

In weighted bit-flipping-based algorithms for low-density parity-check (LDPC) codes, due to the existence of overconfident incorrectly received bits, the metric values of the corresponding bits will always be wrong in the decoding process. Since these bits cannot be flipped, decoding failure results. To solve this problem, an improved parallel weighted bit flipping algorithm is proposed. Specifically, a reliability-saturation strategy is adopted to increase the flipping probability of the overconfident incorrectly received bits. Simulation results show that the error floor of LDPC codes is greatly lowered.

• Journal of IKEEE
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• v.21 no.2
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• pp.130-135
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• 2017

Normally, in data transmission, extra parity bits are added to the input message which were derived from its input and a pre-defined algorithm. The same algorithm is used by the receiver to check the consistency of the delivered information, to determine if it is corrupted or not. It recovers and compares the received information, to provide matching and correcting the corrupted transmitted bits if there is any. This paper aims the following objectives: to use an alternative error detection-correction method, to lessens both the fixed number of the required redundancy bits 'r' in cyclic redundancy checking (CRC) because of the required polynomial generator and the overhead of interspersing the r in Hamming code. The experimental results were synthesized using Xilinx Virtex-5 FPGA and showed a significant increase in both the transmission rate and detection of random errors. Moreover, this proposal can be a better option for detecting and correcting errors.