• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.12C
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• pp.1175-1187
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• 2007

This paper proposes a novel crest factor reduction (CFR) algorithm to be deployed on WCDMA basestation. Generally speaking, it is well described that the reduction of peak-to-average ratio (PAR) yields the possibility of using low cost power amplifier such that the basesation becomes economic However, the simple reduction of PAR could degrade the signal quality measured by either peak code domain error (PCDE) or error vector measurement (EVM), and the level of channel interference constrained by adjacent channel leakage ratio (ACLR). Regarding these imperfections, this paper introduces an effective CFR algorithm in which the function of filter-dependent CFR (FDCFR) incorporated with the histogram-based waterfilling code domain compensation (HBWCDC) carries out. To verify the performance of the proposed CFR technique, substantial simulations including comparative works are conducted with obeying W-CDMA basestation verification specification. To exploit the superiority, the performance of the proposed method is tentatively compared with that associated to the simple memoryless clipping method and the memory-required filter-dependent clipping method.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.16 no.9
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• pp.6254-6259
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• 2015

On the optical system and the system itself of the noise of the noise from the outside always present. This noise is to function as reducing performance of the optical system. Therefore, the probability of error, thereby changing the system. In this paper, the error probability of the optical system due to changes in various values by introducing the characteristic variable the value of the optical system was calculated using the ${\kappa}$-square method. Was confirmed also in accordance with the calculation result is an error probability of the optical system changes, it was confirmed that when the value of the holding case for holding the standard about 400 Lux on the probability of the optical system. This case was found to be an optical system using a light source with a low output, so that means the smaller output is no problem to maintain the error probability value of the optical system is large. This means that more effective and less expensive to implement because it means that the optical system does not require the use of pre-amplifier for amplifying the signal at the receiving end of an optical system using a light source with a low output when the normal case.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.5
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• pp.547-555
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• 2008

This parer proposed the path mismatch detection and compensation algorithm with closed form for linear amplification with non-linear components(LINC) system implementation. The LINC system has a merit of using the high efficient amplifier by transferring the non-constant envelop signal which is high peak to average signal ratio into constant envelop signal. However, the performance degradation is very sensitive to the path mismatch such as an amplitude mismatch and a phase mismatch. In order to improve the path mismatch, the error detection and compensation method is introduced by the use of four test signals. Since the presented method has the closed form solution, the efficient and fast detection is available. The digital-IF structure of LINC system applied by the proposed error detection and compensation algorithm was implemented. The performance was evaluated with the IEEE 802.16 WiMAX baseband sinal which has 7 MHz channel bandwidth and 16-QAM. The Error Vector Magnitude(EVM) of -37.37 dB was obtained through performance test, which meets performance requirement of -24 dB EVM. As a result, the introduced error detection and compensation method was verified to improve the LINC system performance.

• Korean Journal of Optics and Photonics
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• v.5 no.1
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• pp.166-172
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• 1994

The fiber optic receiver, ETRI APD-FET 1.0, is developed for the application of optical communication. This fiber optic receiver includes PD sub-module and pre-amplifier case. A single lens system is introduced for the PD sub-module. The sub-module consists of the avalenche photodiode(APD), GRIN rod lens, and a single mode fiber. The above components are enclosed into the stainless steel 304L housings. By bevelling the fiber end, the single mode fiber provides less than ~ 28 dB of optical return loss. The area of image focus is controlled by adjusting the length of spacer located in-between the fiber and the GRIN rod lens. The laser welding technique is applied to achieve the maximum coupling efficiency for the joining of each housing. In the pre-amplifier case, GaAs FET pre-amplifier workes for photocurrent amplification and the thermister is mounted to control the APD bias. The performance of ETRI APD-FET1.0 shows the sensitivity of - 30.3 dBm at $10^{-10}$ BER(bit error rate) and 2.5 Gbps optical random signal of $2^{23}-1$ word length. The fiber optic receiver is one of the essensial parts of the transmission module for B-ISDN. Also, the above optical packaging technology will be adapted for the developement of 10 Gbps transmission application 2.5 Gbps 5 Gbps

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.12 no.7
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• pp.1086-1093
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• 2001

A new linearization technique for RF high-power amplifiers(HPAs) using n-th order error signal generator (ESGn) is proposed. The n-th order ESG generates an error signal based on the complex envelope transfer characteristics of the HPA, which is combined at the output of the HPA. Therefore, the higher-order nonlinearlities are not affected by the ESG$\_$n/ and the stability of the linearized system is guaranteed due to the inherent open-loop configuration. Moreover, the output delay loss can be avoided, because the error signal is generated with the input signal of the HPA. The IMD(intermodulation distortion) improvement obtained applying the ESG$\_$7/ to 5 W class A HPA in cellular band demonstrates the feasibility of the proposed postdistortion system.

• The KIPS Transactions:PartA
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• v.11A no.2
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• pp.195-202
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• 2004

This paper introduces the design or parallel Pipeline high-speed analog-to-digital converter(ADC) for the high-resolution video applications which require very precise sampling. The overall architecture of the ADC consists of 4-channel parallel time-interleaved 10-bit pipeline ADC structure a]lowing 200MSample/s sampling speed which corresponds to 4-times improvement in sampling speed per channel. Key building blocks are composed of the front-end sample-and-hold amplifier(SHA), the dynamic comparator and the 2-stage full differential operational amplifier. The 1-bit DAC, comparator and gain-2 amplifier are used internally in each stage and they were integrated into single switched capacitor architecture allowing high speed operation as well as low power consumption. In this work, the gain of operational amplifier was enhanced significantly using negative resistance element. In the ADC, a delay line Is designed for each stage using D-flip flops to align the bit signals and minimize the timing error in the conversion. The converter has the power dissipation of 280㎽ at 3.3V power supply. Measured performance includes DNL and INL of +0.7/-0.6LSB, +0.9/-0.3LSB.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.6B
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• pp.1156-1164
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• 1999

In this paper, we have studied the 8 YSB (8 Vestigial Side Band) method which is decided as the standard of modulators for next generation digital TV System. In developing digital TV System, one of the difficult problems is how digital signal can be transmitted to the receiver without any phase distortion. But, phase error is liable to occur by imperfect design, circumstance variation and device degradation. These characteristics result in distortion of 1,0 signal of modulator and interference in adjacent channels. In particular, the interference in modulator of a high power amplifier result in serious problems in adjacent channels. Here we analyzed problems of phase error which are occurred when 8 levels digital signals are modulated to If signal. And we suggested phase error compensation algorithm and discussed the results for adaptation of the algorithm

• Journal of Power Electronics
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• v.15 no.6
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• pp.1673-1681
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• 2015

A low dropout (LDO) regulator with a wide-bandwidth is proposed in this paper. The regulator features a Human Body Model (HBM) 8kV-class high robustness ElectroStatic Discharge (ESD) protection circuit, and two error amplifiers (one with low gain and wide bandwidth, and the other with high gain and narrow bandwidth). The dual error amplifiers are located within the feedback loop of the LDO regulator, and they selectively amplify the signal according to its ripples. The proposed LDO regulator is more efficient in its regulation process because of its selective amplification according to frequency and bandwidth. Furthermore, the proposed regulator has the same gain as a conventional LDO at 62 dB with a 130 kHz-wide bandwidth, which is approximately 3.5 times that of a conventional LDO. The proposed device presents a fast response with improved load and line regulation characteristics. In addition, to prevent an increase in the area of the circuit, a body-driven fabrication technique was used for the error amplifier and the pass transistor. The proposed LDO regulator has an input voltage range of 2.5 V to 4.5 V, and it provides a load current of 100 mA in an output voltage range of 1.2 V to 4.1 V. In addition, to prevent damage in the Integrated Circuit (IC) as a result of static electricity, the reliability of IC was improved by embedding a self-produced 8 kV-class (Chip level) ESD protection circuit of a P-substrate-Triggered Silicon Controlled Rectifier (PTSCR) type with high robustness characteristics.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.1
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• pp.47-52
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• 2004

This paper presents a CMOS optical receiver design featuring wide input dynamic range and low bit error rate suitable for FTTH application. We achieved 60dB input dynamic range for up to 100Mbps by controlling the PMOS feedback resistance of transimpedance preamplifier according to its output signal level. Auto-bias circuit is designed in current mirror configuration to minimize duty error. Circuit simulation has been performed using 2-poly, 3-metal, 0.6um CMOS process parameters. The designed receiver consumes less than 130mW at 100Mbps with 5V power supply.

• Korean Journal of Optics and Photonics
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• v.14 no.4
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• pp.454-459
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• 2003

We report the first demonstration of 10 Gb/s wavelength conversion in a Mach-Zehnder interferometric wavelength converter monolithically integrated with a loss-coupled DFB probe source. The integrated device is fabricated using a BRS (buried ridge stripe) structure with an undoped InP clad layer on the top of a passive waveguide to reduce high propagation loss. The device exhibited a static extinction ratio of 11 dB. Good performance at 10 Gb/s is obtained with an extinction ratio of 7 dB and a power penalty of 2.8 dB at a 10$^{-9}$ bit error rate.