• 한국안전학회지
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• 제15권4호
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• pp.62-68
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• 2000

Static electricity in electronics manufacturing plants causes the economic loss, yet it is one of the least understood and least recognized effects haunting the industry today. Today's challenge in semiconductor devices is to achieve greater functional density pattern and to miniaturize electronic systems of being more fragile by electrostatic discharges(ESD) phenomena. As the use of automatic handling equipment for static-sensitive semiconductor components is rapidly increased, most manufacturers need to be more alert to the problem of ESD. One of the most common causes of electrostatic damage is the direct transfer of electrostatic charge from the human body or a charged material to the static-sensitive devices. To evaluate the ESD hazards by charged human body and devices, in this paper, characteristics of electrostatic attenuation in domestic semiconductor devices is investigated and the voltage to cause electronic component failures is investigated by field-induced charged device model(FCDM) tester. The FCDM simulator provides a fast and inexpensive test that faithfully represents ESD hazards in plants. Also the results obtained in this paper can be used for the prevention of semiconductor failure from ESD hazards.

• 반도체디스플레이기술학회지
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• 제12권3호
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• pp.19-22
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• 2013

The purpose of this study is to develop a system that can monitor the amounts of energy consumption during CVD and etching process for semiconductor manufacturing. Specifically, this system is designed to measure the $CO_2$ emission amounts quantitatively by measuring the flow rate of gas used and amount of power consumed during the processes. The processes of CVD equipment can be classified generally into processing step and cleaning step and all the two steps were monitored. In CVD and etcher equipments, various gases including Ar and $O_2$ are used, but Ar, $O_2$ and He were monitored with the use of the LCI data of Korea Environmental Industry & Technology Institute and carbon emission coefficients of EcoInvent. As a result, it was found that the carbon emission amounts of CVD equipment for Ar, $O_2$ and He were $0.030kgCO_2/min$, $4.580{\times}10^{-3}kgCO_2/min$ and $6.817{\times}10^{-4}kgCO_2/min$, respectively and those of etcher equipment for Ar and $O_2$ are $5.111{\times}10^{-3}kgCO_2/min$ and $7.172kgCO_2/min$, respectively.

• 한국반도체및디스플레이장비학회:학술대회논문집
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• 한국반도체및디스플레이장비학회 2005년도 추계 학술대회
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• pp.102-105
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• 2005

In this study Al electrode for OLED was deposited by FTS(Facing Targets Sputtering) system which can deposit thin films with low substrate damage. The Al thin films were deposited on the cell (LiF/EML/HTL/Bottom electrode) as a function of working gas such as Ar, Kr or mixed gas. Also Al thin films were prepared with working gas pressure (1, 6 mTorr ). The film thickness and I-V curve of Al/cell were evaluated by $\alpha$-step and semiconductor parameter (HP4156A) measurement.

• 반도체디스플레이기술학회지
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• 제21권4호
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• pp.81-85
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• 2022

Mist-CVD is known to have advantages of low cost and high productivity method since the precursor solution is misting with an ultrasonic generator and reacted on the substrate under vacuum-free conditions of atmospheric pressure. However, since the deposition distribution is not uniform, various efforts have been made to derive optimal conditions by changing the angle of the substrate and the position of the outlet to improve the result of the preceding study. Therefore, in this study, a deposition distribution uniformity model was derived through the shape and position of the substrate support and the conditions of inlet flow rate using the particle tracking method of computational fluid dynamics (CFD). The results of analysis were compared with the previous studies through experiment. It was confirmed that the rate of deposition area was improved from 38.7% to 100%, and the rate of deposition uniformity was 79.07% which was higher than the predicted result of simulation. Particle tracking method can reduce trial and error in experiments and can be considered as a reliable prediction method.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2011년도 춘계학술대회
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• pp.136-139
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• 2011

현재의 반도체 검사장비는 테스트 패턴 프로그램을 위한 메모리로 시스템 설계가 간단하고 리프레시가 필요 없는 SRAM(static random access memory) 모듈을 채용하고 있다. 그러나 SRAM 모듈을 이용한 시스템 구성은 용량이 커질수록 장비의 부피가 증가하기 때문에 메모리 대용량화 및 장비의 소형화에 걸림돌이 되고 있다. DRAM(dynamic random access memory)을 이용하여 반도체 검사 장비를 제작할 경우 SRAM 보다 비용과 장비의 면적이 줄어드는 장점이 있지만 DRAM의 특성 상메모리 셀 리프레시가 필요하여 정시성을 보장해야 하는 문제가 있다. 따라서 본 논문에서는 이러한 문제를 해결하기 위해 DDR2 SDRAM(double data rate synchronous dynamic random access memory)을 이용한 비메모리 검사장비에서 정시성을 보장해 주는 알고리즘을 제안하고 알고리즘을 이용한 메모리 컨트롤러를 제작하였다.

• 응용통계연구
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• 제34권1호
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• pp.99-114
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• 2021

반도체 제조 산업에서는 Big Data에 기초한 Smart Factory 도입과 적용이 가시화되면서 생산 공정의 각 단계에서 수집 가능한 다양한 센서(sensor) 데이터를 활용하여 공정 이상 탐지 및 최종 수율 예측 등에 다양한 분석 방법을 시도하고 있다. 현재 반도체 공정은 원료인 잉곳(ingot)에서 패키징(packaging) 작업 이전의 웨이퍼(wafer) 생산까지 500 600개 이상의 세부 공정과 이와 연계된 수천 개의 계측 공정으로 구성된다. 개별 계측 공정 내의 실제 계측 비율은 대상 제품 대비 0.1%에서 최대 5%를 넘지 못하고 계측 시점별로 일정하게 유지할 수 없다. 이러한 이유로 공정 각 단계의 정상 상태를 간접적으로 판단할 수 있는 장비 센서(sensor) 데이터를 활용하여 관리 여부를 판단하고자 하는 노력이 계속되고 있다. 본 연구에서는 장비 센서 데이터 기반의 공정 이상 탐지 프로세스를 정의하고 현재 적용 되고 있는 기술 통계량 기반 진단 방법의 단점을 보완하기 위해 FDA(Functional Data Analysis)방법을 활용하였다. 실제 현장 사례 데이터에 머신러닝을 이용하여 이상 탐지 정확도 비교를 통해 효과성을 검증하였다.

• Journal of Information Processing Systems
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• 제10권3호
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• pp.429-442
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• 2014

In this paper, we investigated the use of seasonal autoregressive integrated moving average (SARIMA) time series models for fault detection in semiconductor etch equipment data. The derivative dynamic time warping algorithm was employed for the synchronization of data. The models were generated using a set of data from healthy runs, and the established models were compared with the experimental runs to find the faulty runs. It has been shown that the SARIMA modeling for this data can detect faults in the etch tool data from the semiconductor industry with an accuracy of 80% and 90% using the parameter-wise error computation and the step-wise error computation, respectively. We found that SARIMA is useful to detect incipient faults in semiconductor fabrication.

• 반도체디스플레이기술학회지
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• 제19권3호
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• pp.55-60
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• 2020

The hard mask photo-resist strip inspection system for the semiconductor wafer manufacturing process inspects the position of the circuit pattern formed on the wafer by measuring the distance from the edge of the wafer to the strip processing area. After that, it is an inspection system that enables you to check the process status in real time. Process defects can be significantly reduced by applying a tester that has not been applied to the existing wafer strip process, edge etching process, and wafer ashing process. In addition, it is a technology for localizing semiconductor process inspection equipment that can analyze the outer diameter of the wafer and the state of pattern formation, which can secure process stability and improve wafer edge yield.

• 반도체디스플레이기술학회지
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• 제9권4호
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• pp.71-76
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• 2010

According to recent changes in industry for semiconductor devices, a low-temperature treatment has become a necessity. These changes relate to size refinement and the development of new materials. While variation in cooling efficiency does not affect the yield when using a high-temperature treatment, uniform cooling efficiency is necessary avoid "inconsistencies/bends" in low temperature treatments. However it is difficult to increase temperature stabilization in low temperature treatments. In this paper, using CFD (Computer Fluid Dynamics), we analyze and manipulate the design and input of the low-temperature system to attempt to control for temperature variations within the quartz tube, of which airflow appears to be a predominant factor. This simulation includes variable inputs such as airflow rate, head pressure, and design manipulations in the S.C.U. (Super Cooling Unit).

• 한국산업융합학회 논문집
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• 제15권1호
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• pp.37-42
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• 2012

Trends in semiconductor equipment industry are to reduce the cost of producing semiconductor, semiconductor process development, facility development, and the minimum investment in terms of cost and quality. Semiconductor equipments are being considered to review and development is proceeding at the same time. In the first part of the semiconductor assembly process, in which the importance of die bonding process is emerging, a wide leadframe type die bonding machine is demanded for productivity. Die bonding machine was designed through experiments and by trial and error. It costs a lot of time and financial burden. The purpose of this study is to solve these problems by using the CAE tool 3G. By using finite element method, thermal analysis of die bonding machine to the various widths leadframe die bonder machine rail is performed for design.