• 한국진공학회:학술대회논문집
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• 한국진공학회 2015년도 제49회 하계 정기학술대회 초록집
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• pp.86.1-86.1
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• 2015

As the feature size of Si-based semiconductor shrinks to nanometer scale, we are facing to the problems such as short channel effect and leakage current. One of the solutions to cope with those issues is to bring III-V compound semiconductors to the semiconductor structures, because III-V compound semiconductors have much higher carrier mobility than Si. However, introduction of III-V semiconductors to the current Si-based manufacturing process requires great challenge in the development of process integration, since they exhibit totally different physical and chemical properties from Si. For example, epitaxial growth, surface preparation and wet etching of III-V semiconductors have to be optimized for production. In addition, oxidation mechanisms of III-V semiconductors should be elucidated and re-growth of native oxide should be controlled. In this study, surface preparation methods of various III-V compound semiconductors such as GaAs, InAs, and GaSb are introduced in terms of i) how their surfaces are modified after different chemical treatments, ii) how they will be re-oxidized after chemical treatments, and iii) is there any effect of surface orientation on the surface preparation and re-growth of oxide. Surface termination and behaviors on those semiconductors were observed by MIR-FTIR, XPS, ellipsometer, and contact angle measurements. In addition, photoresist stripping process on III-V semiconductor is also studied, because there is a chance that a conventional photoresist stripping process can attack III-V semiconductor surfaces. Based on the Hansen theory various organic solvents such as 1-methyl-2-pyrrolydone, dimethyl sulfoxide, benzyl alcohol, and propylene carbonate, were selected to remove photoresists with and without ion implantation. Although SPM and DIO3 caused etching and/or surface roughening of III-V semiconductor surface, organic solvents could remove I-line photoresist without attack of III-V semiconductor surface. The behavior of photoresist removal depends on the solvent temperature and ion implantation dose.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2015년도 제49회 하계 정기학술대회 초록집
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• pp.62-62
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• 2015

In this study, we study the effects of CF4 plasma treatment on the characteristics of enhancement mode (E-mode) AlGaN/GaN high electron mobility transistors (HEMTs). The CF4 plasma is generated by inductively coupled plasma reactive ion etching (ICP-RIE) system. The CF4 gas is decomposed into fluorine ions by ICP-RIE and then fluorine ions will effect the AlGaN/GaN interface to inhibit the electron transport of two dimension electron gas (2DEG) and increase channel resistance. The CF4 plasma method neither like the recessed type which have to utilize Cl2/BCl3 to etch semiconductor layer nor ion implantation needed high power to implant ions into semiconductor. Both of techniques will cause semiconductor damage. In the experiment, the CF4 treatment time are 0, 50, 100, 150, 200 and 250 seconds. It was found that the devices treated 100 seconds showed best electric performance. In order to prove fluorine ions existing and CF4 plasma treatment not etch epitaxial layer, the secondary ion mass spectrometer confirmed fluorine ions truly existing in the sample which treatment time 100 seconds. Moreover, transmission electron microscopy showed that the sample treated time 100 seconds did not have etch phenomena. Atomic layer deposition is used to grow Al2O3 with thickness 10, 20, 30 and 40 nm. In electrical measurement, the device that deposited 20-nm-thickness Al2O3 showed excellent current ability, the forward saturation current of 210 mA/mm, transconductance (gm) of 44.1 mS/mm and threshold voltage of 2.28 V, ION/IOFF reach to 108. As IV concerning the breakdown voltage measurement, all kinds of samples can reach to 1450 V.

• 한국전기전자재료학회논문지
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• 제19권7호
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• pp.605-610
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• 2006

We have investigated $Al_{0.25}Ga_{0.75}As/In_{0.2}Ga_{0.8}As$ structures for pseudomorphic high electron mobility transistor(pHEMT), which were grown by molecular beam epitaxy(MBE) and consequently annealed by rapid thermal anneal(RTA), using Hall measurement, photoluminescence, and transmission electron microscopy (TEM). According to intensity and full-width at half maximum maintained stable at the same energy level, the quantized energy level in $Al_{0.25}Ga_{0.75}As/In_{0.2}Ga_{0.8}As$ quantum wells was independent of the RTA conditions. However, the Hall mobility was decreased from $6,326cm^2/V.s\;to\;2,790cm^2/V.s\;and\;2,078cm^2/V.s$ after heat treatment respectively at $500^{\circ}C\;and\;600^{\circ}C$. The heat treatment which is indispensable during the fabrication procedure would cause catastrophic degradation in electrical transport properties. TEM observation revealed atomically non-uniform interfaces, but no dislocations were generated or propagated. From theoretical consideration about the mobility changes owing to inter-diffusion, the degraded mobility could be directly correlated to the interface scattering as long as samples were annealed below $600^{\circ}C$ lot 1 min.

• 한국세라믹학회지
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• 제40권5호
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• pp.455-459
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• 2003

LPE(Liquid Phase Epitaxial)법을 이용하여 성장시킨 B $i_2$S $r_2$Ca(C $u_{1-x}$ N $i_{x}$ )$_2$ $O_{8+}$$\delta$/ 막(film)을 break junction 법을 이용하여 터널링 분광을 측정하였다. Ni 조성비 $\chi$$_{L}$의 증가에 따라 에너지 간격 2$\Delta$의 크기는 증가하였다. 에너지 간격 2$\Delta$(4.2 K)는 54.4~64 meV, 2$\Delta$/ $k_{B}$ $T_{c}$ $^{zero}$는 7.36~10.14로 BCS 이론에 의한 값 보다 큰 결과를 얻었다. 융액(melting solution) 속의 Ni 조성비 $\chi$$_{L}$의 증가에 따라, 임계온도 $T_{c}$ $^{zero}$와 격자상수 c-축의 길이는 감소하는 경향을 보였다.을 보였다.$^{zero}$와 격자상수 c-축의 길이는 감소하는 경향을 보였다.

• 한국결정성장학회지
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• 제10권2호
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• pp.111-115
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• 2000

Ba과 Ti의 금속 유기 화합물을 이용하여 (100) $SrTiO_3$ 기판 위에 $BaTIO_3$ 박막을 코팅-열분해법으로 제조하였다. $450^{\circ}C$에서 사전 열처리한 비정질상의 박막은 $2\times 10^{-4}$ atm으로 조정된 산소 분압 하에서 $700^{\circ}C$ 이상의 온도로 열처리함으로써 결정화되었다. $800^{\circ}C$ 이하에서 제조한 박막의 기판에 수직한 면의 격자상수는 cubic $BaTIO_3$의 a 값에 가까우면 $800^{\circ}C$ 이하에서 제조한 박막의 tetragonal $BaTIO_3$ 의 a 값에 가까 웠다. 박막과 기판의 정렬상태를 XRD $\beta$ scan과 pole-figure로 분석한 결과 $BaTIO_3$ 박막은 $SrTiO_3$ 기판과 에피택시 관계가 있었다. $800^{\circ}C$에서 열처리한 박막의 표면은 0.4${\mu}m$ 정도의 섬 형태의 입자로 구성되어 있었고 약 0.8$\mu\textrm{m}$의 두께를 가진 단면은 구형의 입자가 층을 이루고 있었다.

• 한국결정성장학회지
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• 제13권5호
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• pp.247-253
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• 2003

본 연구에서는 반응기의 유입 확대부의 형상이 반응기 내의 유동 및 증착특성에 미치는 영향을 연구하기 위하여 수평형 MOCVD 반응기에서 TMGa와 $AsH_3$로부터의 GaAs 증착에 관한 수치적 연구를 수행하였다. 두 개의 기하학적인자(확대각, 확대부 형상)가 증착률, 증착률 균일도. 유속 균일도, 압력강하에 미치는 영향을 연구하였다 웨이퍼 위에서의 증착률 균일도, 평균증착률, 유속 균일도를 고려한 결과, 직선형 확대부의 최적 확대각은 $50^{\circ}$∼$55^{\circ}$이며 포물선형 확대부의경우, $40^{\circ}$∼$45^{\circ}$이다. 또한 확대부의 확대각의 변화는 평균증착률 보다 증착률의 균일도에 큰 영향을 미치고 있음을 알 수 있으며 직선확대부보다 포물선형의 확대부에서 더 민감하게 나타남을 알 수 있었다.

• 한국초전도ㆍ저온공학회논문지
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• 제22권3호
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• pp.7-12
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• 2020

Electromechanical properties of REBCO CC tapes are known to be limited by defects (cracks) that form in the brittle REBCO layer. These defects could be inherently acquired during the CC tapes' manufacturing process, such as slitting, and which can be initiated at the CC tapes' edges. If propagated and long enough, they are believed to cause critical current degradation and can substantially decrease the delamination strength of CC tapes. Currently, commercially available CC tapes from various manufacturers utilize different growth techniques for depositing the REBCO layers on the substrates in their CC tapes preparation. Their epitaxial techniques, unfortunately, cannot perfectly avoid the formation of particles, in which sometimes acts as current blocking defects, known as outgrowths. Collective research regarding the composition, size, and formation of these particles for various CC tapes with different deposition techniques are particularly uncommon in a single study. Most importantly, these particles might interact in one way or another to the existing cracks. Therefore, systematic investigation on the interactions between the cracks' development mechanism and particles on the REBCO superconducting layers of practical CC tapes are of great importance, especially in the design of superconducting devices. Here, a proper etching process was employed for the CC tapes to expose and observe the REBCO layers, clearly. The scanning electron microscope, field emission scanning microscope, and energy-dispersive x-ray spectroscopy were utilized to observe the interactions between cracks and particles in various practical CC tapes. Particle compositions were identified whether as non-superconducting or superconducting and in what manner it interacts with the cracks were studied.

• 한국재료학회지
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• 제24권12호
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• pp.645-651
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• 2014

GaN is most commonly used to make LED elements. But, due to differences of the thermal expansion coefficient and lattice mismatch with sapphire, dislocations have occurred at about $109{\sim}1010/cm^2$. Generally, a low temperature GaN buffer layer is used between the GaN layer and the sapphire substrate in order to reduce the dislocation density and improve the characteristics of the thin film, and thus to increase the efficiency of the LED. Further, patterned sapphire substrate (PSS) are applied to improve the light extraction efficiency. In this experiment, using an AlN buffer layer on PSS in place of the GaN buffer layer that is used mainly to improve the properties of the GaN film, light extraction efficiency and overall properties of the thin film are improved at the same time. The AlN buffer layer was deposited by using a sputter and the AlN buffer layer thickness was determined to be 25 nm through XRD analysis after growing the GaN film at $1070^{\circ}C$ on the AlN buffer CPSS (C-plane Patterned Sapphire Substrate, AlN buffer 25 nm, 100 nm, 200 nm, 300 nm). The GaN film layer formed by applying a 2 step epitaxial lateral overgrowth (ELOG) process, and by changing temperatures ($1020{\sim}1070^{\circ}C$) and pressures (85~300 Torr). To confirm the surface morphology, we used SEM, AFM, and optical microscopy. To analyze the properties (dislocation density and crystallinity) of a thin film, we used HR-XRD and Cathodoluminescence.

• 한국산학기술학회논문지
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• 제11권10호
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• pp.3917-3922
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• 2010

본 논문은 U-band(40~60 GHz)대역에 최적화된 epitaxial로 pHEMT(Pseudomorphic High Electron Mobility Transistor)을 제작, 대신호 모델링하여 특성분석 및 60 GHz 대역의 3단 증폭기를 MMIC(Monolithic Microwave Integrated Circuit)로 설계 제작하였다. 본 논문에 사용된 pHEMT는 $0.12\;{\mu}m$의 게이트 길이와 총 게이트 면적 $100\;{\mu}m$, $200\;{\mu}m$를 사용하여 대신호 모델링하였으며 설계시 안정도의 향상을 위하여 부궤환회로와 함께 MIM(Metal-Insulator-Metal) 커패시터 대신 MCLF(Microstriop Coupled Line Filter)를 사용하여 안정도를 향상시켰다. 제작결과 크기가 $2.5{\times}1.5mm^2$이고 소모된 전류는 약 40 mA, 동작주파수 59.5 ~ 60.5 GHz에서 이득 19.9 dB ~ 18.6 dB, 입력정합특성 -14.6 dB ~-14.7 dB, 출력정합 특성 -11.9 dB ~-16.3 dB와 출력 -5 dBm의 특성을 얻었다.

• 한국재료학회:학술대회논문집
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• 한국재료학회 2003년도 추계학술발표강연 및 논문개요집
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• pp.62-62
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• 2003

금속-실리콘간 화합물인 실리사이드 중에서, 코발트다이실리사이드(CoSi$_2$)는 비저항이 낮고 선폭이 좁아짐에 따라 면저항이 급격히 증가하는 선폭의존성이 없으며 화학적으로 안정한 재료로 현재 널리 이용되고 있는 재료이다. 또한, 실리콘 (100) 기판과 에피택셜하게 성장한 CoSi$_2$는 우수한 열안정성 과 낮은 juction leakage의 특성을 가지며, shallow junction 형성을 가능하게 하는 많은 장점을 가지고 있어 각광받고 있다. 그러나 순수한 Co의 증착 후속 열처리에 의해 형성된 CoSi$_2$는 (110), (111), (221)등의 다양한 결정방위를 가지게 되어 에피택셜 하게 형성되기 어렵다. 현재까지 Ti, Ta, Zr과 화학 산화막 등의 확산 방지막을 이용하여 에피 택셜하게 성장시키는 많은 방법들이 연구되어 왔으며, 최근에는 본 연구실에서 반응성화학기상증착법으로 Co-C 박막을 증착하여 in-Situ로 에피택셜 CoSi$_2$를 형성하는 새로운 방법을 보고하였다. 본 연구는 반응성 스퍼터링에 의해 증착된 Co-N 박박으로부터 후속 열처리를 통하여 에피택셜 CoSi$_2$를 성장시키는 새로운 방법을 제시하고자 한다. Co-N 박박은 Ar과 $N_2$의 혼합가스 분위기 속에서 Co를 스퍼터링하여 증착하였다. 증착시 혼합가스 내의 $N_2$함량의 변화에 따라 다양한 Co-N 박막이 형성됨을 확인하였다. 후속열처리시 Co-N 박막의 산화를 방지하기 위하여 Ti층을 마그네트론 스퍼터링으로 증착하였으며, Ar 분위기에서 온도에 따른 ex-situ RTA 열처리를 통하여 에피택셜 CoSi$_2$를 성장시킬 수 있었다. 이러한 에피택셜 CoSi$_2$는 특정 한 Ar/$N_2$ 비율 내에서 성장이 가능하였으며, 약 $600^{\circ}C$이상의 열처리 온도에서 관찰되었다.