• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.8
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• pp.38-43
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• 1998

An analytical model for the surface field distribution of the RESURF (reduced surface field)LD(lateral double-diffused) MOS is presented in terms of the doping concentration, the thickness of the n epi layer, the p substrate concentration, and the epi layer length. The reuslts are used to determine the breakdown voltage due to the surface field as a function of the epi layer length. The maximum breakdown voltage of the device is found to be that of the vertical n$^{+}$n$^{[-10]}$ p$^{[-10]}$ junction. Analytical results of the breakdown voltage vs. the epi layer length agree well with the numerical simulation results using MEDICI.I.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.07a
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• pp.101-102
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• 2005

SiC lateral power semiconductor device has high breakdown voltage and low on-state voltage drop due to the material characteristics. And, because the high breakdown voltage can be obtained, RESURF technique is mostly used in silicon power semiconductor devices. In this paper, we presents the electrical characteristics of the 4H-SiC RESURF LDMOSFET as a function of the epi-layer length, concentration and thickness. 240~780V of breakdown voltage can be obtained as a function of epi-layer length and thickness with same epi-layer concentration.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.10
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• pp.79-86
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• 1994

Gain-guided broad-area single quantum well separate confinement heterostructure diode lasers have been fabricated from structures grown by metal organic vapor phase epitaxy. The active layer of the epi-structure is InGaAs emitting 962-965nm and the guiding layer GaAs. The channel width is fixed to 150${\mu}$m and the cavity length varys within the range of 300~800${\mu}$m. For uncoated LD's, the output power of 0.7W has been obtaained at a pulsed current level of 2A, which results about 60% external quantum efficiency. The threshold current density is 200A/cm$^{2}$ for the cavity lengths of 800.mu.m LD's. The stain effect upon the transparent current density has been observed. The internal quantum efficiency is expected to be 88% and the internal loss to be 18$cm^{-1}$. The beam divergence has been measured to be 7$^{\circ}$to lateral and 40$^{\circ}$to transverse direction. finally, 1.2W continuous-wave output power has been obtained at a current level of 2A for AR/HR coated LD's die-bonded on Cu heat-sink and cooled by TEC.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.12
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• pp.130-135
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• 1995

GaAs power MESFET's with 0.5 .mu.m gate length using a conventional UV lithography and angle evaporations are fabricated and then DC and RF characteristics are measured and carefully analyzed. The 0.5$\mu$m GaAs power MESFET's are fabricated on epi-wafers which have an undoped GaAs layer inbetween n+ and n GaAs layers grown by MBE, and by the processes such as an image reversal(IR), air-bridge, and our developed 0.5 .mu.m gate fabrication techniques. The total gate widths of the fabricated 0.5$\mu$m GaAs power MESFETs are 0.6-3.0 mm, the current saturation of them 80-400 mA, the maximum linear and RF output power of them 60-265 mW. The current gain cut-off frequencies for the 0.5$\mu$m GaAs power MESFETs varies 13-16 GHz. For the test frequency of 10 GHz the maximum unilateral transducer power gains and the power added efficiencies of the GaAs power devices are 7.0-2.5 dB and 35.68-30.76 %, respectively.

• Journal of Radiation Industry
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• v.6 no.1
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• pp.31-40
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• 2012

There are two methods to fabricate the readout electronic to a large-area CMOS image sensor (LACIS). One is to design and manufacture the sensor part and signal processing electronics in a single chip and the other is to integrate both parts with bump bonding or wire bonding after manufacturing both parts separately. The latter method has an advantage of the high yield because the optimized and specialized fabrication process can be chosen in designing and manufacturing each part. In this paper, LACIS chip, that is optimized design for the latter method of fabrication, is presented. The LACIS chip consists of a 3-TR pixel photodiode array, row driver (or called as a gate driver) circuit, and bonding pads to the external readout ICs. Among 4 types of the photodiode structure available in a standard CMOS process, $N_{photo}/P_{epi}$ type photodiode showed the highest quantum efficiency in the simulation study, though it requires one additional mask to control the doping concentration of $N_{photo}$ layer. The optimized channel widths and lengths of 3 pixel transistors are also determined by simulation. The select transistor is not significantly affected by channel length and width. But source follower transistor is strongly influenced by length and width. In row driver, to reduce signal time delay by high capacitance at output node, three stage inverter drivers are used. And channel width of the inverter driver increases gradually in each step. The sensor has very long metal wire that is about 170 mm. The repeater consisted of inverters is applied proper amount of pixel rows. It can help to reduce the long metal-line delay.