• Journal of Internet Computing and Services
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• v.20 no.3
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• pp.85-92
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• 2019

In this paper, we extract the quantitative relation data of activities from the workflow event log file recorded in the XES standard format and connect them to rediscover the workflow process model. Extract the workflow process patterns and proportions with the rediscovered model. There are four types of control-flow elements that should be used to extract workflow process patterns and portions with log files: linear (sequential) routing, disjunctive (selective) routing, conjunctive (parallel) routing, and iterative routing patterns. In this paper, we focus on four of the factors, disjunctive routing, and conjunctive path. A framework implemented by the authors' research group extracts and arranges the activity data from the log and converts the iteration of duplicate relationships into a quantitative value. Also, for accurate analysis, a parallel process is recorded in the log file based on execution time, and algorithms for finding and eliminating information distortion are designed and implemented. With these refined data, we rediscover the workflow process model following the relationship between the activities. This series of experiments are conducted using the Large Bank Transaction Process Model provided by 4TU and visualizes the experiment process and results.

• Journal of the Korean Society of Systems Engineering
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• v.8 no.1
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• pp.9-19
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• 2012

The Light Rail Transit Project is a large scaled project which takes several years in building a system. After construction, LRT system is operating for several tens of years. For these characteristics, the right application of systems engineering to LRT project greatly effects the project success. In this paper, we present systems engineering application model to LRT project i.e. SELRT which include systems engineering technical process, core technology management process, project support process. SELRT also has a module for the exchange of outputs in SE tool and PM tool. Systems engineering processes in SELRT mainly base on ISO/IEC 15288. In future, we expand the range of SE processes and improve the usability in SELRT. We expect that this model will contribute to improve the efficiency in LRT project and to success the LRT project.

• Journal of Digital Convergence
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• v.10 no.1
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• pp.317-321
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• 2012

There are SW engineering absence that cause the SW quality and Productivity Increase problems during software development project. Are exist necessity awareness of SW engineering growth and professional SW engineering manpower education. This paper define the SW Engineering standard Curriculum that establishment continuous growth and suggest guide manpower practical use guide. When performing the projects, we can suggest for SW Engineering professionals acquisition and standard to solve them by using Standard Curriculum for Software Engineering, which can strengthen manpower capacity the organization SW Engineering. This research provides solution of SW Process Curriculum about SW Development Process and SW Quality.

• Journal of the Korean Society of Systems Engineering
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• v.9 no.1
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• pp.47-53
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• 2013

The object of this study is to define systematically for outputs of Verification Process among the system life cycle process based on ISO/IEC 15288 for power supply system, which is one of the importance sub-systems to configure the LRT system. Furthermore, to prevent various problem in advance that can occur in the Transition LRT's power supply to be completed Integration. For this purpose, traceability of verification requirement and outputs. should be managed to use verification for system requirement and data processing tool. by system engineering techniques of system life cycle process based on ISO/IEC 15288 to LRT system.

• Nuclear Engineering and Technology
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• v.48 no.4
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• pp.1047-1057
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• 2016

Design engineering process for field programmable gate array (FPGA)-based reactor trip functions are developed in this work. The process discussed in this work is based on the systems engineering approach. The overall design process is effectively implemented by combining with design and implementation processes. It transforms its overall development process from traditional V-model to Y-model. This approach gives the benefit of concurrent engineering of design work with software implementation. As a result, it reduces development time and effort. The design engineering process consisted of five activities, which are performed and discussed: needs/systems analysis; requirement analysis; functional analysis; design synthesis; and design verification and validation. Those activities are used to develop FPGA-based reactor bistable trip functions that trigger reactor trip when the process input value exceeds the setpoint. To implement design synthesis effectively, a model-based design technique is implied. The finite-state machine with data path structural modeling technique together with very high speed integrated circuit hardware description language and the Aldec Active-HDL tool are used to design, model, and verify the reactor bistable trip functions for nuclear power plants.

• IE interfaces
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• v.17 no.4
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• pp.414-425
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• 2004

This study presents the decision of priority for optimal design guide to improve disassembly process. Disassembly process is divided into recognition, transfer and disassembly of assembly point and recognition, transfer and remove of grasp point. Significant influential factors are derived from analyzing the above process. And those factors are used for making the check list to evaluate the properties of parts in each process. Furthermore, the weight with considering disassembly process is also used to determine weight of each process. On the base of the above sequence, qualitative score of disassemblability of each process that is enabled to compare different disassembly processes can be acquired. Ultimately the score helps to decide the priority of design guide for disassembly process.

• Journal of Electrical Engineering and Technology
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• v.10 no.3
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• pp.1138-1143
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• 2015

Effects of fabrication process variations on impedance of microelectrodes integrated on a neural probe were examined through equivalent circuit modeling and SPICE simulation. Process variation and the corresponding range were estimated based on experimental data. The modeling results illustrate that the process variation induced by metal etching process was the dominant factor in impedance variation. We also demonstrate that the effect of process variation is frequency dependent. Another process variation that was examined in this work was the thickness variation induced by deposition process. The modeling results indicate that the effect of thickness variation on impedance is negligible. This work provides a means to predict the variations in impedance values of microelectrodes on neural probe due to different process variations.

• International Journal of Automotive Technology
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• v.7 no.2
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• pp.217-226
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• 2006

To maintain competitiveness in the modern automotive market, it is important to carry out process planning concurrently with new car development processes. Process planners need to make decisions concurrently and collaboratively in order to reduce manufacturing preparation time for developing a new car. Automated generation of a simulation model by using the integrated process plan database can reduce time consumed for carrying out a simulation and allow a consistent model to be used throughout. In this research, we developed a web-based system for concurrent and collaborative process planning and flow analysis for an automotive general assembly using web, database, and simulation technology. A single integrated database is designed to automatically generate simulation models from process plans without having to rework the data. This system enables process planners to evaluate their decisions quickly, considering various factors, and easily share their opinions with others. By using this collaborative system, time and cost put into the assembly process planning can be reduced and the reliability of the process plan would be improved.

• Journal of Korean Society of Industrial and Systems Engineering
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• v.25 no.2
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• pp.1-10
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• 2002

Process capability indices are widely used in industries and quality assurance system. In past years, process capability analysis have been used to characterize process performance on the basis of univariate quality characteristics. However, in actual manufacturing industrial, statistical process control (SPC) often entails characterizing or assessing processes or products based on more than one engineering specification or quality characteristic. Therefore, the analysis have to be required a multivariate statistical technique. This paper introduces to multivariate capability indices and then selects a multivariate process capability index incorporated both the process variation and the process deviation from target among these indices under the multivariate normal distribution. We propose a new multivariate capability index $MC_{pm}^+$ using quality loss function instead of the process variation and this index is compared with the proposed indices when quality characteristics are independent and dependent of each other.

• Transactions on Electrical and Electronic Materials
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• v.13 no.3
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• pp.129-135
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• 2012

A number of surface mount technology (SMT) process variables including land design are considered for minimizing tombstone defect in flexible printed circuit assembly in high volume manufacturing. As SMT chip components have been reduced over the past years with their weights in milligrams, the torque that once helped self-centering of chips, gears to tombstone defects. In this paper, we have investigated the correlation of the assembly process variables with respect to the tombstone defect by employing statistically designed experiment. After the statistical analysis is performed, we have setup hypotheses for the root causes of tombstone defect and derived main effects and interactions of the process parameters affecting the hypothesis. Based on the designed experiments, statistical analysis was performed to investigate significant process variable for the purpose of process control in flexible printed circuit manufacturing area. Finally, we provide beneficial suggestions for find-pitch PCB design, screen printing process, chip-mounting process, and reflow process to minimize the tombstone defects.