• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.10
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• pp.2324-2330
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• 2010

In middle and high school to learn the principles of fluid mechanics to Experiments in space and time constraints and difficulties for the study of the principles of fluid mechanics to the problem is superficial. In this paper, Pascal's principles, Archimedes' Principle, Bernoulli's Theorem, etc. learning about the fluid mechanics and implemented in Web Browser, In connection with flash and HTML, web simulation is to implement. Web Based Instruction program that implemented a comparative analysis became an effect of 15% to industrial total high school students in satisfaction, Interest, Achievement. The fluid mechanics education through engineering design and web design through the actual web server is implemented on the Internet over broadband. Department of Education, this study the fluid mechanics and the Internet will contribute to the development of distance education.

• Archives of design research
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• v.14 no.2
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• pp.57-66
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• 2001

This research was carried with emphasis on the technical contents of lighting design which had various knowledge system in the educational viewpoint. First of all, phisiolosical and physical factors were considered with the process of vision between human and light. Next, components of attributes in the lighting fixture were prescribed to analyze concept of the fixture. Finally, I proposed educational program in the instruction to meet the purpose of this research. As a result, in overall research concerning the basic direction and structure, instruction should have balance to reconcile theory and practice about lighting. Second, in terms of expansion of cognition about lighting, experimental education that is considered with interface is needed to make practical verification through relationship with man-made environment and scientific data.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.3
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• pp.333-340
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• 2017

In this paper, we describe HW/SW co-optimizations for reconfigurable application specific instruction-set processors (ASIPs). Based on our previous very long instruction word (VLIW) ASIP, the proposed framework realizes various forward error-correction (FEC) algorithms for wireless communication systems. In order to enhance the energy efficiency, we newly introduce several design methodologies including high-radix algorithms, task-level out-of-order executions, and intensive resource allocations with loop-level rescheduling. The case study on the radix-4 turbo decoding shows that the proposed techniques improve the energy efficiency by 3.7 times compared to the previous architecture.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.4
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• pp.559-566
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• 2002

n this paper, we propose a WBI(Web Based Instruction) for individualized learning using push and pull technologies with WWW(World Wide Web). As well as push End pull technologies, the proposing system is implemented with JSP(Java Server Page) and JDBC(Java Database Connectivity) of java technologies based on the client/server envirionments for the purpose of providing practical lectures to students.

• Transactions on Electrical and Electronic Materials
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• v.13 no.6
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• pp.278-282
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• 2012

Photovoltaic systems have emerged to be one of the cleanest energy systems. Therefore, many large scale solar parks and PV farms have been built to prepare for the post fossil fuel ages. However, due to their large scale, to efficiently manage and operate PV systems, they need to be visually monitored within the range of infrared ray through the Internet. To satisfy this need, the efficient implementation of a high performance video compression standard is required. This paper therefore presents an implementation of H.264 motion estimation, which is one of the most data-intensive and complicated functions in H.264. To achieve this, this work implements vector instructions in hardware and incorporates them in a generic RISC processor architecture, thus increasing the processing speed while minimizing hardware and software design efforts. Extensive simulation results show that this proposed implementation can process motion estimations up to 13 times faster.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.5 no.7
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• pp.1332-1339
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• 2001

SoC(System on Chip) technology is widely used in the field of embedded systems by providing high flexibility for a specific application domain. An important aspect of development any new embedded system is verification which usually requires lengthy software and hardware co-design. To reduce development cost of design effort, the instruction set of microprocessor must be suitable for a high level language compiler. And FPGA prototype system could be derived and tested for design verification. In this paper, we propose a 16 bit FPGA microprocessor, which is tentatively-named EISC16, based on an EISC(Extendable Instruction Set Computer) architecture for embedded applications. The proposed EISC16 has a 16 bit fixed length instruction set which has the short length offset and small immediate operand. A 16 bit offset and immediate operand could be extended using by an extension register and an extension flag. We developed a cross C/C++ compiler and development software of the EISC16 by porting GNU on an IBM-PC and SUN workstation and compared the object code size created after compiling a C/C. standard library, concluding that EISC16 exhibits a higher code density than existing 16 microprocessors. The proposed EISC16 requires approximately 6,000 gates when designed and synthesized with RTL level VHDL at Xilinix's Virtex XCV300 FPGA. And we design a test board which consists of EISC16 ROM, RAM, LED/LCD panel, periodic timer, input key pad and RS-232C controller. 11 works normally at 7MHz Clock.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.12
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• pp.2691-2697
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• 2010

Shader instructions and Compiler are designed for supporting 3D graphic shader 3.0 API. Variable-length instructions are proposed to reduce the size of hardware of graphic processor in SIMD structure by shortening the length of instructions. The designed shader compiler supports variable and two phased structured instructions, and can be programmable at ESSL level. Conformance Test proposed by Khronos group is accomplished to verify the design result of instructions and complier. The test result shows overall average 37% performance improvement at the 16 functions of basic GL shader.

• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.666-669
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• 2002

A microprocessor with genetic instructions such as crossover, mutation and inversion is proposed. The processor is modeled using VHDL, synthesized to a schematic and implemented on a FPGA. The control path is implemented with a microprogram consisting of about 15032-bit microwords, and the operation of each instruction is checked through simulation.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.7 no.8
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• pp.1809-1815
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• 2003

This paper presents a human friendly system using fuzzy inference as a Part of study to embody intelligent ship. We also build intelligent ship's steering system to take advantage of speech recognition that is a part of the human friendly interface. It can bring an effect such as labor decrement in ship. In order to design the voice instruction based ship's steering gear control system, we build of the voice instruction based learning(VIBL) system based on speech recognition and intelligent learning method at first. Next, we design an quartermaster's operation model by fuzzy inference and construct PC based remote control system. Finally, we applied the unposed control system to the miniature ship and verified its effectiveness.

• JSTS:Journal of Semiconductor Technology and Science
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• v.5 no.4
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• pp.221-228
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• 2005

In this work, our goal is to develop a fast and accurate power model of the ARM926EJ-S processor in the industrial design environment. Compared with existing work on processor power modeling which focuses on the power states of processor core, our model mostly focuses on the cache power model. It gives more than 93% accuracy and 1600 times speedup compared with post-layout gate-level power estimation. We also address two practical issues in applying the processor power model to the real design environment. One is to incorporate the power model into an existing commercial instruction set simulator. The other is the re-characterization of power model parameters to cope with different gate-level netlists of the processor obtained from different design teams and different fabrication technology.