• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.7
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• pp.1296-1302
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• 2016

A hardware implementation of ultra-lightweight block cipher algorithm PRESENT that was specified as a block cipher standard for lightweight cryptography ISO/IEC 29192-2 is described in this paper. Two types of crypto-core that support master key size of 80-bit are designed, one is for encryption-only function, and the other is for encryption and decryption functions. The designed PR80 crypto-cores implement the basic cipher mode of operation ECB (electronic code book), and it can process consecutive blocks of plaintext/ciphertext without reloading master key. The PR80 crypto-cores were designed in soft IP with Verilog HDL, and they were verified using Virtex5 FPGA device. The synthesis results using $0.18{\mu}m$ CMOS cell library show that the encryption-only core has 2,990 GE and the encryption/decryption core has 3,687 GE, so they are very suitable for IoT security applications requiring small gate count. The estimated maximum clock frequency is 500 MHz for the encryption-only core and 444 MHz for the encryption/decryption core.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.8
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• pp.67-74
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• 2008

A compact and high-performance AES(Advanced Encryption Standard) encryption/decryption processor is designed by applying various hardware sharing and optimization techniques. In order to achieve minimized hardware complexity, sharing the S-Boxes for round transformation with the key scheduler, as well as merging and reusing datapaths for encryption and decryption are utilized, thus the area of S-Boxes is reduced by 25%. Also, the S-Boxes which require the largest hardware in AES processor is designed by applying composite field arithmetic on $GF(((2^2)^2)^2)$, thus it further reduces the area of S-Boxes when compared to the design based on $GF(2^8)$ or $GF((2^4)^2)$. By optimizing the operation of the 64-bit round transformation and round key scheduling, the round transformation is processed in 3 clock cycles and an encryption of 128-bit data block is performed in 31 clock cycles. The designed AES processor has about 15,870 gates, and the estimated throughput is 412.9 Mbps at 100 MHz clock frequency.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.19 no.2
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• pp.9-17
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• 2019

In this paper, we propose an attribute-based broadcast encryption algorithm that can be applied to satellite broadcasting network. The encryption algorithm is a cryptographic method by which a carrier(sender) can transmit contents efficiently and securely to a plurality of legitimate users through satellites. An attribute-based encryption algorithm encrypts contents according to property of contents or a user, In this paper, we combine effectively two algorithms to improve the safety and operability of satellite broadcasting network. That is, it can efficiently transmit ciphertexts to a large number of users, and has an advantage in that decoding can be controlled by combining various attributes. The proposed algorithm reduces the network load by greatly reducing the size of the public key, the private key and the cipher text in terms of efficiency, and the decryption operation amount is reduced by half to enable fast decryption, thereby enhancing the operability of the user.

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.944-947
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• 2002

We implemented a cryptoprocessor with a on-the-fly key scheduler which performs forward key scheduling for encryption and reverse key scheduling for decryption. This scheduler makes the fast generation of the key value and eliminates the memory for software key scheduler. The 128-bit Rijndael processor is implemented based on the proposed architecture using Verilog-HDL and targeted to Xilinx XCV1000E FPGA device. As a result, the 128-bit Rijndael operates at 38.8MHz with on-the-fly key scheduler and consumes 11 cycles for encryption and decryption resulting in a throughput of 451.5Mbps

• Journal of Korea Multimedia Society
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• v.9 no.10
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• pp.1371-1379
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• 2006

This paper suggests the padding algorithm using padding character length to concatenate more than one string without side-effect. Most existing padding algorithms padding null character in the empty location could not discriminate the real string from the padded character. To overcome this problem, in this paper, the padded character contains pad character length information. This mechanism is working better than NULL or '00' padding cases. The suggested padding algorithm could be effective for data encryption and decryption algorithms.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.7 no.7
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• pp.1478-1482
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• 2003

In this paper. Rijndael cipher algorithm is implemented by a hardware. It was selected as the AES(Advanced Encryption Standard) by NIST. It has structure that round operation divided into 2 subrounds and subrounds are pipelined to calculate efficiently. It takes 5 clocks for one-round. The AES-128 cipher algorithm is implemented for hardware by ALTERA FPGA, and, analyzed the performance. The AES-128 cipher algorithm has approximately 424 Mbps encryption rate for 166Mhz max clock frequency. In case of decryption, it has 363 Mbps decryption rate fu 142Mhz max clock frequency. In case of cipher core, it has 320Mbps encryptionㆍdecryption rate for 125Mhz max clock frequency.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.12 no.1
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• pp.43-54
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• 2002

McEliece introduced a public-key cryptosystem based on Algebraic codes, specially binary classical Goppa which have a good decoding algorithm and vast number of inequivalent codes with given parameters. And the advantage of this system low cost of their encryption and decryption procedures compared with other public-key systems specially RSA, ECC based on DLP(discrete logarithm problem). But in [1], they resent new attack based on probabilistic algorithm to find minimum weight codeword, so for a sufficient security level, much larger parameter size [2048, 1608,81]is required. Then the big size of public key make McEliece PKC more inefficient. So in this paper, we will propose New Type PKC using q-ary Hyperelliptic code so that with smaller parameter(1 over 3) but still work factor as hi인 as McEliece PKC and faster encryption, decryption can be maintained.

• Korean Journal of Mathematics
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• v.30 no.3
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• pp.533-538
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• 2022

Cryptography is one of the most essential developing areas, which deals with the secure transfer of messages. In recent days, there are more number of algorithms have been evolved to provide better security. This work is also such an attempt. In this paper, an algorithm is presented for encryption and decryption which employs the matrix Q^p* and the well- known equation x² - py² = 1 where p is a prime.

• Journal of Korea Multimedia Society
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• v.25 no.8
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• pp.983-990
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• 2022

In this paper, we implemented a hierarchical encryption system using two-step phase-shifting digital holography(PSDH) technology based on XOR and scramble operations. The proposed encryption system is a system that authenticates access through the issuance of an encryption key for access to individual laboratories, department offices, and universities. In the encryption process, we proposed a double encryption method using XOR and scramble operation with digital technology and two-step phase-shifting digital holography with optical technology. In the two-step PSDH process, an new method of determining the reference wave intensity without measuring it by using random common object image gererated from digital encryption process was also proposed. In the decryption process, the process is performed in the reverse order of encryption process. And only when the various key information used in the encryption process is correct, the encrypted information can be decrypted, so that the user can access the desired place. That is, there is a feature that can hierarchically control the space that can be accessed according to the type of key issued in the proposed encryption system. Through the computer simulation, the feasibility of the proposed hierarchical encryption system was confirmed.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.9 no.11
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• pp.4680-4700
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• 2015

Broadcast encryption is an efficient way to distribute confidential information to a set of receivers using broadcast channel. It allows the broadcaster to dynamically choose the receiver set during each encryption. However, most broadcast encryption schemes in the literature haven't taken into consideration the receiver's privacy protection, and the scanty privacy preserving solutions are often less efficient, which are not suitable for practical scenarios. In this paper, we propose an efficient dynamic anonymous broadcast encryption scheme that has the shortest ciphertext length. The scheme is constructed over the composite order bilinear groups, and adopts the Lagrange interpolation polynomial to hide the receivers' identities, which yields efficient decryption algorithm. Security proofs show that, the proposed scheme is both secure and anonymous under the threat of adaptive adversaries in standard model.